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Patent Agency Ranking
公开(公告)号：US20160370839A1
公开(公告)日：2016-12-22
申请号：US15255791
申请日：2016-09-02
Applicant: Intel Corporation
Inventor： Tapan A. Ganpule , Inder M. Sodhi , Yair Talker , Inbar Falkov , Tanveer R. Khondker
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/08 , G06F1/10 , G06F1/3287 , G06F1/3296 , Y02D10/172
Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
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公开(公告)号：US09965019B2
公开(公告)日：2018-05-08
申请号：US15255791
申请日：2016-09-02
Applicant: Intel Corporation
Inventor： Tapan A. Ganpule , Inder M. Sodhi , Yair Talker , Inbar Falkov , Tanveer R. Khondker
CPC classification number: G06F1/324 , G06F1/08 , G06F1/10 , G06F1/3287 , G06F1/3296 , Y02D10/172
Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
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3.发明授权公开(公告)号：US11327523B2
公开(公告)日：2022-05-10
申请号：US16799480
申请日：2020-02-24
Applicant: Intel Corporation
Inventor： Eyal Fayneh , Elias Nassar , Inbar Falkov , Ramkumar Krithivasan , Vijay K. Vuppaladadium , Miguel A. Corvacho Hernandez , Samer Nassar , Yair Talker
Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
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4.发明授权公开(公告)号：US10571953B2
公开(公告)日：2020-02-25
申请号：US15642109
申请日：2017-07-05
Applicant: Intel Corporation
Inventor： Eyal Fayneh , Elias Nassar , Inbar Falkov , Ramkumar Krithivasan , Vijay K. Vuppaladadium , Miguel A. Corvacho Hernandez , Samer Nasser , Yair Talker
Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.
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公开(公告)号：US09459689B2
公开(公告)日：2016-10-04
申请号：US14138852
申请日：2013-12-23
Applicant: Intel Corporation
Inventor： Tapan A. Ganpule , Inder M. Sodhi , Yair Talker , Inbar Falkov , Tanveer R. Khondker
CPC classification number: G06F1/324 , G06F1/08 , G06F1/10 , G06F1/3287 , G06F1/3296 , Y02D10/172
Abstract: In one embodiment, a processor includes a plurality of functional units each to independently execute instructions and a clock distribution circuit having a clock signal generator to generate a clock signal. The clock distribution circuit is coupled to receive a first operating voltage from a first voltage rail and the functional units are coupled to independently receive at least one second operating voltage from one or more second voltage rails. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个功能单元，每个功能单元各自独立地执行指令，以及具有时钟信号发生器的时钟分配电路以产生时钟信号。 时钟分配电路被耦合以从第一电压轨道接收第一工作电压，并且功能单元被耦合以独立地从一个或多个第二电压轨道接收至少一个第二工作电压。 描述和要求保护其他实施例。
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