公开(公告)号：US11327523B2

公开(公告)日：2022-05-10

申请号：US16799480

申请日：2020-02-24

Applicant: Intel Corporation

Inventor： Eyal Fayneh ,  Elias Nassar ,  Inbar Falkov ,  Ramkumar Krithivasan ,  Vijay K. Vuppaladadium ,  Miguel A. Corvacho Hernandez ,  Samer Nassar ,  Yair Talker

IPC: G06F1/06 ,  G06F1/08 ,  G06F1/04 ,  G06F1/12

Abstract: A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

公开(公告)号：US09791834B1

公开(公告)日：2017-10-17

申请号：US15393115

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Elias Nassar ,  Samer Nassar ,  Eyal Fayneh ,  Rotem Banin ,  Ofir Degani ,  Inbar Falkov

IPC: H03M1/50 ,  G04F10/00

CPC classification number: G04F10/005 ,  G04G5/00

Abstract: A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

公开(公告)号：US10659061B2

公开(公告)日：2020-05-19

申请号：US16472835

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Elias Nassar ,  Eyal Fayneh ,  Inbar Falkov ,  Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Samer Nassar

IPC: H03D3/24 ,  H03L7/091 ,  H03L7/099

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

公开(公告)号：US20190334533A1

公开(公告)日：2019-10-31

申请号：US16472835

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Elias Nassar ,  Eyal Fayneh ,  Inbar Falkov ,  Elan Banin ,  Rotem Banin ,  Ofir Degani ,  Samer Nassar

IPC: H03L7/091 ,  H03L7/099

Abstract: A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.