公开(公告)号：US09936570B2

公开(公告)日：2018-04-03

申请号：US14570791

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Min Wang ,  Russell N. Shryock

IPC: H05K1/02 ,  H01P3/02 ,  H05K1/11

CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

公开(公告)号：US20160172734A1

公开(公告)日：2016-06-16

申请号：US14570791

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Min Wang ,  Russell N. Shryock

IPC: H01P3/08

CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

Abstract translation: 公开了一种互连拓扑，其包括多个互连，每个互连使用通孔耦合在一起，其中至少两个通孔相对于彼此交错。 在一个实施例中，互连拓扑包括衬底，通过多层上的衬底布线的多个信号迹线以及多个通孔，其中每个通孔耦合一对信号迹线以形成多个不同层之间的互连， 并且其中一对通孔包括第一通孔以承载正差分信号通路和第二通孔，以携带耦合到信号迹线的负差分信号以形成差分信号对。 差分第一和第二通孔相对于彼此交错。