公开(公告)号：US20220366630A1

公开(公告)日：2022-11-17

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20190066256A1

公开(公告)日：2019-02-28

申请号：US16170597

申请日：2018-10-25

Applicant: INTEL CORPORATION

Inventor： SAURABH SHARMA ,  ABHISHEK VENKATESH ,  TRAVIS T. SCHLUESSLER ,  THOMAS F. RAOUX ,  RAHUL P. SATHE ,  JON HASSELGREN

IPC: G06T1/20 ,  G06F9/38 ,  G06T15/00 ,  G06F8/41

Abstract: Techniques to improve graphics processing unit (GPU) performance by introducing specialized code paths to process frequent common values are described. A shader compiler can determine instruction that, during operation, may output a common value and can introduce an enhanced shader instruction branch to process the common value to reduce overall computational requirements to execute the shader.

公开(公告)号：US20210272349A1

公开(公告)日：2021-09-02

申请号：US17306769

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200043124A1

公开(公告)日：2020-02-06

申请号：US16543849

申请日：2019-08-19

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  JORGE F. GARCIA PABON ,  VIKRANTH VEMULAPALLI ,  CHANDRA S. GURRAM ,  ADITYA NAVALE ,  SAURABH SHARMA

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38

Abstract: A processing apparatus is described. The apparatus includes a graphics processing unit (GPU), including a register file having a plurality of channels to store data and an execution unit to examine data at each of the plurality of channels, read a data value from a first of the plurality of channels upon a determination that each of the plurality of channels has the same data and execute a single input multi data (SIMD) instruction based on the data value.