公开(公告)号：US20210090207A1

公开(公告)日：2021-03-25

申请号：US17061296

申请日：2020-10-01

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20200211147A1

公开(公告)日：2020-07-02

申请号：US16236305

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06T15/00 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20230244609A1

公开(公告)日：2023-08-03

申请号：US18148749

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： ZACK S. WATERS ,  TRAVIS SCHLUESSLER ,  MICHAEL APODACA ,  ANKUR SHAH

IPC: G06F12/0882 ,  G06F12/0837 ,  G06F12/1045 ,  G06F11/30 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/06

CPC classification number: G06F12/0882 ,  G06F12/0837 ,  G06F12/1054 ,  G06F12/1063 ,  G06F11/3006 ,  G06F9/5016 ,  G06F9/4411 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0607

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

公开(公告)号：US20220327655A1

公开(公告)日：2022-10-13

申请号：US17724299

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： MICHAEL DOYLE ,  TRAVIS SCHLUESSLER ,  GABOR LIKTOR ,  ATSUO KUWAHARA ,  JEFFERSON AMSTUTZ

IPC: G06T1/20 ,  G06F16/901 ,  G06F9/38 ,  G06F9/50 ,  G06T15/00

Abstract: An apparatus comprising a sorting unit to sort primitives of a graphics image, the primitives to be grouped, each group to form a first level node of a hierarchical acceleration structure; a parallel reconfigurable clustering array to construct the hierarchical acceleration structure, the parallel reconfigurable clustering array comprising a plurality of processing clusters, each cluster comprising: parallel efficiency analysis circuitry to evaluate different groupings of the first level nodes for a next level of the hierarchical acceleration structure to determine efficiency values for the different groupings; and node merge circuitry to merge the first level nodes based on the efficiency values to form second level nodes.

公开(公告)号：US20200175643A1

公开(公告)日：2020-06-04

申请号：US16208715

申请日：2018-12-04

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  JASON SURPRISE ,  PETER DOYLE

IPC: G06T1/20 ,  G06F9/50

Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.

公开(公告)号：US20220366630A1

公开(公告)日：2022-11-17

申请号：US17876358

申请日：2022-07-28

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20200211259A1

公开(公告)日：2020-07-02

申请号：US16235391

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MICHAEL APODACA ,  CARSTEN BENTHIN ,  KAI XIAO ,  CARSON BROWNLEE ,  TIMOTHY ROWLEY ,  JOSHUA BARCZAK ,  TRAVIS SCHLUESSLER

IPC: G06T15/06 ,  G06F7/14 ,  G06F16/901 ,  G06F9/38

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20200211253A1

公开(公告)日：2020-07-02

申请号：US16236176

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： GABOR LIKTOR ,  KARTHIK VAIDYANATHAN ,  JEFFERSON AMSTUTZ ,  ATSUO KUWAHARA ,  MICHAEL DOYLE ,  TRAVIS SCHLUESSLER

IPC: G06T15/00 ,  G06T15/06 ,  G06T1/60

Abstract: Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

公开(公告)号：US20210272349A1

公开(公告)日：2021-09-02

申请号：US17306769

申请日：2021-05-03

Applicant: Intel Corporation

Inventor： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC: G06T15/00 ,  G06T15/40 ,  G06T15/80

Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20210263853A1

公开(公告)日：2021-08-26

申请号：US16802427

申请日：2020-02-26

Applicant: Intel Corporation

Inventor： ZACK S. WATERS ,  TRAVIS SCHLUESSLER ,  MICHAEL APODACA ,  ANKUR SHAH

IPC: G06F12/0882 ,  G06F12/0837 ,  G06F12/1045 ,  G06F12/06 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F11/30

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.