公开(公告)号：US20220084589A1

公开(公告)日：2022-03-17

申请号：US16948300

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Sandeep Kumar Guliani ,  Mase J. Taub ,  DerChang Kau ,  Ashir G. Shah

IPC: G11C13/00

Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

公开(公告)号：US11900998B2

公开(公告)日：2024-02-13

申请号：US16948300

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Balaji Srinivasan ,  Sandeep Kumar Guliani ,  Mase J. Taub ,  Derchang Kau ,  Ashir G. Shah

IPC: G11C8/08 ,  G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/0026

Abstract: A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.

公开(公告)号：US20230289099A1

公开(公告)日：2023-09-14

申请号：US17693199

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Yasir Mohsin Husain ,  Xuming Zhao ,  Kevin E. Arendt ,  Sandeep Kumar Guliani

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C13/0004 ,  G06F3/0604 ,  G06F3/0679 ,  G11C13/0026 ,  G11C13/0028

Abstract: An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.