公开(公告)号：US20230317154A1

公开(公告)日：2023-10-05

申请号：US17706943

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Yasir Mohsin Husain ,  Xuming Zhao

IPC: G11C13/00

CPC classification number: G11C13/0028 ,  G11C13/0038 ,  H01L45/1233 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

Abstract: Techniques for dynamically biasing memory cells are disclosed. In the illustrative embodiment, a source follower sets a voltage on a wordline of a memory cell. A bias voltage on the gate of the source follower can be temporarily increased in order to charge the wordline more quickly. In some embodiments, for a read operation, after a demarcation voltage has been applied to the memory cell for the memory cell to change its resistance if it is set, the bias voltage on the gate of the source follower is decreased in order to prevent the memory cell from changing its resistance while the current through the memory cell is being read. In some embodiments, a current mirror can be activated in order to bleed off charge from the wordline to lower the voltage more quickly.

公开(公告)号：US20230289099A1

公开(公告)日：2023-09-14

申请号：US17693199

申请日：2022-03-11

Applicant: Intel Corporation

Inventor： Yasir Mohsin Husain ,  Xuming Zhao ,  Kevin E. Arendt ,  Sandeep Kumar Guliani

IPC: G06F3/06 ,  G11C13/00

CPC classification number: G06F3/0659 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0097 ,  G11C13/0004 ,  G06F3/0604 ,  G06F3/0679 ,  G11C13/0026 ,  G11C13/0028

Abstract: An apparatus, system and method. The apparatus is to be coupled to a memory array of a memory device. The apparatus, in response to a determination of a set command to be implemented on first memory cells of the memory array, is to control an execution of a set pre-read operation on the first memory cells by causing application, by a voltage source, of a first demarcation voltage VDM0 across each of the first memory cells during a set pre-read time period. The apparatus is further to, in response to a determination of a reset command to be implemented on second memory cells of the memory array, control an execution of a reset pre-read operation on the second memory cells by causing application, by the voltage source, of a second demarcation voltage VDM3 across each of the second memory cells during a reset pre-read time period, wherein the set pre-read time period and the reset pre-read time period do not overlap, the voltage source to supply a single voltage value at any given time.