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公开(公告)号：US09612647B2
公开(公告)日：2017-04-04
申请号：US14074985
申请日：2013-11-08
Applicant: Intel Corporation
Inventor： Sathyanarayanan Gopal , Sanjib Basu , Pravas Pradhan , Prakash K. Radhakrishnan
CPC classification number: G06F1/3265 , G06F1/26 , G06F1/32 , G06F1/3287 , Y02D10/153 , Y02D10/171
Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.
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