公开(公告)号：US20190012981A1

公开(公告)日：2019-01-10

申请号：US15641463

申请日：2017-07-05

Applicant: Intel Corporation

Inventor： Aruna Kumar L S ,  Anoop Karunan ,  Sanjib Basu ,  Sunil Kumar CR

IPC: G09G5/00 ,  H04L29/06

Abstract: Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.

公开(公告)号：US10943558B2

公开(公告)日：2021-03-09

申请号：US15199125

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Aruna Kumar L. S. ,  Sunil Kumar C. R. ,  Sanjib Basu ,  Prakash K. Radhakrishnan

IPC: G09G5/00 ,  G09G5/36

Abstract: An integrated circuit is described. The integrated circuit includes a display controller having a driver. The display controller is configurable to select two or more display interfaces. The driver is designed to drive respective signals for the two or more display interfaces through a single output.

公开(公告)号：US09612647B2

公开(公告)日：2017-04-04

申请号：US14074985

申请日：2013-11-08

Applicant: Intel Corporation

Inventor： Sathyanarayanan Gopal ,  Sanjib Basu ,  Pravas Pradhan ,  Prakash K. Radhakrishnan

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3265 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  Y02D10/153 ,  Y02D10/171

Abstract: By partitioning the source PHY of a physical layer interface, such as a DisplayPort interface, between multiple power domains, dynamic switching between various power modes with faster entry and exit latency can be achieved in some embodiments. In some embodiments, the scheme may be hardware initiated and autonomous in nature. A controller can switch the PHY in and out of the various power consumption modes, dependent on usage scenarios.

公开(公告)号：US10950198B2

公开(公告)日：2021-03-16

申请号：US15641463

申请日：2017-07-05

Applicant: Intel Corporation

Inventor： Aruna Kumar L S ,  Anoop Karunan ,  Sanjib Basu ,  Sunil Kumar C R

IPC: G09G5/00 ,  H04L29/06 ,  G09G5/36 ,  G09G3/20 ,  H04L7/00

Abstract: Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.