公开(公告)号：US20210058334A1

公开(公告)日：2021-02-25

申请号：US16547482

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John GRETH ,  Arvind SRINIVASAN ,  David ARDITTI ILITZKY ,  Robert SOUTHWORTH ,  Gaspar MORA PORTA ,  Scott DIESING ,  Bongjin JUNG ,  Prasad SHABADI

IPC: H04L12/867 ,  H04L12/911 ,  H04L12/863 ,  H04L12/865

Abstract: Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.