公开(公告)号：US20210058343A1

公开(公告)日：2021-02-25

申请号：US16546993

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John GRETH ,  Arvind SRINIVASAN ,  Robert SOUTHWORTH ,  David ARDITTI ILITZKY ,  Bongjin JUNG ,  Gaspar MORA PORTA

IPC: H04L12/935 ,  H04L12/947 ,  H04L12/24 ,  H04L29/06

Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.

公开(公告)号：US20200278665A1

公开(公告)日：2020-09-03

申请号：US16634542

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： David ARDITTI ILITZKY ,  Ignacio J. ALVAREZ ,  Julio C. ZAMORA ESQUIVEL ,  Paulo LOPEZ MEYER

IPC: G05B19/418 ,  G06K9/62 ,  H04L29/08 ,  G06F17/16

Abstract: An apparatus for autonomous vehicles includes a perception pipeline having independent classification processes operating in parallel to respectively identify objects belonging to a specific object type based on sensor data flows from multiple ones of a plurality of different types of sensors. The apparatus also includes a sensor monitoring stage to operate in parallel with the perception pipeline and to use the sensor data flows to estimate and track a confidence level of each of the plurality of different types of sensors, and nullify a deficient sensor when the confidence level associated with the deficient sensor fails to meet a confidence threshold.

公开(公告)号：US20230123665A1

公开(公告)日：2023-04-20

申请号：US17892862

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Ignacio ALVAREZ ,  David ARDITTI ILITZKY ,  Patrick Andrew MEAD ,  Javier FELIP LEON ,  David GONZALEZ AGUIRRE

IPC: G01S7/40 ,  G01S17/86 ,  G01S7/497 ,  G01S13/58 ,  G01S13/86 ,  G01S13/931 ,  G01S17/58

Abstract: Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.

公开(公告)号：US20210058334A1

公开(公告)日：2021-02-25

申请号：US16547482

申请日：2019-08-21

Applicant: Intel Corporation

Inventor： John GRETH ,  Arvind SRINIVASAN ,  David ARDITTI ILITZKY ,  Robert SOUTHWORTH ,  Gaspar MORA PORTA ,  Scott DIESING ,  Bongjin JUNG ,  Prasad SHABADI

IPC: H04L12/867 ,  H04L12/911 ,  H04L12/863 ,  H04L12/865

Abstract: Examples described herein provide a packet ingress and egress system with a memory buffer in a network device. The ingress and egress system can generate a time stamp for one or more received packets at an ingress port, allocate a received packet to a queue among multiple queues, and permit egress of a packet from a queue. An ingress port can have one or more queues allocated to store received packets. An egress port can use the one or more queues from which to egress packets. A maximum size of a queue is set as the allocated memory region size divided by the number of ingress ports that use the allocated memory region. An egress arbiter can apply an arbitration scheme to schedule egress of packets in time stamp order.

公开(公告)号：US20180351590A1

公开(公告)日：2018-12-06

申请号：US15778240

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： David ARDITTI ILITZKY ,  Rocio HERNANDEZ FABIAN

IPC: H04B1/10 ,  H04L25/02 ,  H04L25/03 ,  H04L25/08

CPC classification number: H04B1/1027 ,  H04B1/10 ,  H04B1/123 ,  H04L25/024 ,  H04L25/03 ,  H04L25/08

Abstract: A communication device is provided that includes a receiver configured to receive a signal. The communication device further includes a determination circuit configured to determine an interference estimation signal of the received signal based on a first signal sample of the received signal and on an interference signal model. The communication device further includes a correction circuit configured to determine a corrected interference estimation signal based on the determined interference estimation signal and on a second signal sample of the received signal. The communication device further includes a subtraction circuit configured to subtract the corrected interference estimation signal from the received signal.