公开(公告)号：US20230387074A1

公开(公告)日：2023-11-30

申请号：US17825350

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Nitin Deshpande ,  Satish Damaraju ,  Scott Siers ,  Kai-Chiang Wu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513

Abstract: An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

公开(公告)号：US20230205094A1

公开(公告)日：2023-06-29

申请号：US17561524

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Scott Siers ,  Satish Damaraju ,  Christopher Pelto

IPC: G03F7/20 ,  H01L23/48 ,  H01L23/498

CPC classification number: G03F7/70475 ,  H01L23/481 ,  H01L23/49816

Abstract: Compute complexes, base dies, and methods related to leveraging reticle stitching for improved device interconnects are discussed. A base die includes first and second regions having device layers, lower level metallization layers, and through vias fabricated using the same reticles. In the first region, a first subset of the through vias are contacted by higher metallization layers and, in the second region, a second distinct subset of the through vias are contacted by higher metallization layers such that the first and second metallization layers provide unique routing through vias having shared layouts and relative locations in the first and second regions.