公开(公告)号：US20230387073A1

公开(公告)日：2023-11-30

申请号：US17825340

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Kai-Chiang Wu ,  Han-wen Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513

Abstract: An integrated circuit assembly may be formed with a bridge incorporated into at least one level structure of the integrated circuit assembly, which electrically interconnects at least two integrated circuit devices in another level structure of the integrated circuit assembly. In one example, the integrated circuit assembly may include a first level structure that comprises at least a first integrated circuit device and a second integrated circuit device, and a second level structure comprising at least one integrated circuit device electrically attached to the first integrated circuit device of the first level structure and the bridge forming an electrical attachment between the first integrated circuit device of the first level structure and the second integrated circuit device of the first level structure.

公开(公告)号：US20230387074A1

公开(公告)日：2023-11-30

申请号：US17825350

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Nitin Deshpande ,  Satish Damaraju ,  Scott Siers ,  Kai-Chiang Wu

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/49816 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/16 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2225/06513

Abstract: An integrated circuit assembly may be formed having a first level structure that comprises a monolithic substrate with a first reticle zone including integrated circuitry and a second reticle zone including integrated circuitry, and a second level structure comprising at least one integrated circuit device electrically attached to the integrated circuitry of the first reticle zone of the first level structure and a bridge electrically attaching the integrated circuitry of the first reticle zone of the first level structure and the integrated circuitry of the second reticle zone of the first level structure.

公开(公告)号：US20240332126A1

公开(公告)日：2024-10-03

申请号：US18129654

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Andy Wei ,  Po-Yao Ke ,  Kai-Chiang Wu ,  Han-wen Lin ,  Klaus Max Schruefer ,  Dean Huang ,  Hsin-Hua Wang

IPC: H01L23/373 ,  H01L23/367

CPC classification number: H01L23/3737 ,  H01L23/3677 ,  H01L23/3735 ,  H01L23/481

Abstract: Thermal dissipation and grounding of integrated circuit (IC) devices with backside power delivery networks are discussed. An IC device layer between frontside and backside interconnect sections, composed mostly of an insulating material, is coupled to a crystalline heat spreader or a metal thermal ground layer by an array of thermal pillars extending through the insulating material. The crystalline heat spreader layer may include one or more thermal sensors, such as thermal sensing diodes, also coupled to the IC device layer by one or more thermal pillars. The IC device layer and crystalline layers are coupled by a hybrid bond, which forms the thermal pillars through a continuous section of the insulating material.