公开(公告)号：US11620256B2

公开(公告)日：2023-04-04

申请号：US17732308

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/08 ,  G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F17/18 ,  G06F12/0802 ,  G06F7/544 ,  G06F7/575 ,  G06F12/02 ,  G06F12/0866 ,  G06F12/0875 ,  G06F12/0895 ,  G06F12/128 ,  G06F12/06 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F12/0811 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06F12/0871 ,  G06F12/0862 ,  G06F12/0897 ,  G06F9/50 ,  G06F12/0804 ,  G06F12/0882 ,  G06F12/0891 ,  G06F12/0893 ,  G06T15/06 ,  G06N3/08

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US12210477B2

公开(公告)日：2025-01-28

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20220261347A1

公开(公告)日：2022-08-18

申请号：US17732308

申请日：2022-04-28

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter,, JR. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：US20220179787A1

公开(公告)日：2022-06-09

申请号：US17428530

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Altug Koker ,  Joydeep Ray ,  Ben Ashbaugh ,  Jonathan Pearce ,  Abhishek Appu ,  Vasanth Ranganathan ,  Lakshminarayanan Striramassarma ,  Elmoustapha Ould-Ahmed-Vall ,  Aravindh Anantaraman ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Yoav Harel ,  Arthur Hunter, Jr. ,  Brent Insko ,  Scott Janus ,  Pattabhiraman K ,  Mike Macpherson ,  Subramaniam Maiyuran ,  Marian Alin Petre ,  Murali Ramadoss ,  Shailesh Shah ,  Kamal Sinha ,  Prasoonkumar Surti ,  Vikranth Vemulapalli

IPC: G06F12/0802 ,  G06F9/30

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.