公开(公告)号：US20190146335A1

公开(公告)日：2019-05-16

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20180323104A1

公开(公告)日：2018-11-08

申请号：US15772013

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Todd R. YOUNKIN ,  Eungnak HAN ,  Shane M. HARLSON ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/027 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16

CPC classification number: H01L21/76897 ,  G03F7/0002 ,  G03F7/0045 ,  G03F7/16 ,  H01L21/0274 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/48 ,  H01L23/532 ,  H01L23/5329 ,  H01L23/53295

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.