公开(公告)号：US20210057230A1

公开(公告)日：2021-02-25

申请号：US16954419

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Tayseer MAHDI

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/033 ,  C23C16/26 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417

Abstract: Carbon-based dielectric materials for semiconductor structure fabrication, and the resulting structures, are described. In an example, method of patterning a layer for a semiconductor structure includes forming a plurality of trenches in a dielectric layer above a semiconductor layer above a substrate to form a patterned dielectric layer. The method also includes filling the plurality of trenches with an adamantane-based carbon hardmask material. The method also includes removing the patterned dielectric layer selective to the adamantane-based carbon hardmask material. The method also includes using the adamantane-based carbon hardmask material to pattern the semiconductor layer.

公开(公告)号：US20190318959A1

公开(公告)日：2019-10-17

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20160351449A1

公开(公告)日：2016-12-01

申请号：US15237542

申请日：2016-08-15

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Rami HOURANI ,  Eungnak HAN ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/76897 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/02118 ,  H01L21/0271 ,  H01L21/31051 ,  H01L21/31127 ,  H01L21/76822 ,  H01L21/76834 ,  H01L23/528 ,  H01L23/5328 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a second patterned region. A first directed self assembly alignment promotion material is formed selectively over the first patterned region without using lithographic patterning. The method also includes forming an assembled layer over the directed self assembly alignment promotion layer by directed self assembly. A plurality of assembled structures are formed that each include predominantly a first type of polymer over the first directed self assembly alignment promotion material. The assembled structures are each adjacently surrounded by predominantly a second different type of polymer over the second patterned region. The first directed self assembly alignment promotion material has a greater chemical affinity for the first type of polymer than for the second different type of polymer.

Abstract translation: 一个方面的方法包括在具有第一图案化区域和第二图案化区域的基底的表面上形成定向自组装对准促进层。 选择性地在第一图案化区域上形成第一定向自组装对准促进材料，而不使用平版印刷图案。 该方法还包括通过定向自组装在定向自组装对准促进层上形成组装层。 形成多个组装结构，每个组合结构主要包括第一类型的自组装排列促进材料上的第一类聚合物。 组装的结构在第二图案化区域上主要围绕第二种不同类型的聚合物。 第一定向自组装校准促进材料对于第一类聚合物具有比对于第二种不同类型的聚合物更大的化学亲和力。

公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20190043731A1

公开(公告)日：2019-02-07

申请号：US16075555

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20180204797A1

公开(公告)日：2018-07-19

申请号：US15575808

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI

IPC: H01L23/522 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53295

Abstract: Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.

公开(公告)号：US20220130719A1

公开(公告)日：2022-04-28

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210082800A1

公开(公告)日：2021-03-18

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20180323104A1

公开(公告)日：2018-11-08

申请号：US15772013

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Todd R. YOUNKIN ,  Eungnak HAN ,  Shane M. HARLSON ,  James M. BLACKWELL

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/027 ,  G03F7/00 ,  G03F7/004 ,  G03F7/16

CPC classification number: H01L21/76897 ,  G03F7/0002 ,  G03F7/0045 ,  G03F7/16 ,  H01L21/0274 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/48 ,  H01L23/532 ,  H01L23/5329 ,  H01L23/53295

Abstract: Fabrication schemes based on triblock copolymers for forming self-aligning vias or contacts for back end of line interconnects, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate. The method also includes forming a triblock copolymer layer above the lower metallization layer. The method also includes segregating the triblock copolymer layer to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer, where the third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

公开(公告)号：US20180294167A1

公开(公告)日：2018-10-11

申请号：US15769017

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  James M. BLACKWELL

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L21/3105

Abstract: Described herein are structures and methods for preparing photobuckets for lithography, e.g. photolithography or electron-beam lithography. One method includes arranging photobuckets on a material to be etched using lithography and providing a layer of a first material at least on inner side walls of the photobuckets, followed by filling the photobuckets with a second material. The second material is more lithosensitive than the first material and the first material could be not lithosensitive at all. Layering each photobucket from the inner side wall(s) of the photobucket towards the center of the photobucket with materials that are increasingly more lithosensitive results in an improved control of lithographic patterning by reducing or eliminating edge placement errors of accidentally exposing photobuckets that should not have been exposed.