公开(公告)号：US20230421040A1

公开(公告)日：2023-12-28

申请号：US17851997

申请日：2022-06-28

申请人： Intel Corporation

发明人： Tamir Salus ,  Shunjiang Xu ,  Christopher Schaef

IPC分类号： H02M1/00 ,  H02M1/088 ,  H02M3/155

CPC分类号： H02M1/0043 ,  H02M1/088 ,  H02M3/155 ,  H02M1/0012

摘要： Techniques and mechanisms for facilitating a scalable delivery of current to an inductor of a voltage regulator. In an embodiment, a hardware interface of integrated circuit (IC) die accommodates coupling of the IC die to multiple inductors. The hardware interface comprises contacts which are each to couple the IC die to a respective one of the multiple inductors. A phase circuit of the IC die includes multiple cells which are each coupled to a different respective contact of a plurality of contacts of the hardware interface. A digital controller of the IC die is operable to select any of various combinations of the multiple cells each to conduct a respective current with a corresponding one of the plurality of contacts. In another embodiment, the plurality of contacts are arranged as a multi-row, multi-column array.

公开(公告)号：US20240297586A1

公开(公告)日：2024-09-05

申请号：US18177426

申请日：2023-03-02

申请人： Intel Corporation

发明人： Keng Chen ,  Shunjiang Xu ,  Christopher Schaef ,  Tamir Salus ,  Kishan Joshi ,  Arvind Raghavan ,  Huanhuan Zhang

IPC分类号： H02M3/158 ,  G06F1/26

CPC分类号： H02M3/1584 ,  G06F1/26

摘要： Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. The other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.

公开(公告)号：US20210408784A1

公开(公告)日：2021-12-30

申请号：US16913887

申请日：2020-06-26

申请人： Intel Corporation

发明人： Aman Sewani ,  Nazar Haider ,  Lan D. Vu ,  Steven S. Poon ,  Shunjiang Xu

IPC分类号： H02H9/00

摘要： Some embodiments include apparatuses having an input node; an electrostatic discharge protection circuitry including a first diode including a cathode coupled to the input node, and an anode coupled to a ground node; a second diode including an anode coupled to the input node, and a cathode coupled to a circuit node; a clamp circuit coupled to the circuit node; and a current limiting circuit coupled between the circuit node and a supply node.