公开(公告)号：US20220199468A1

公开(公告)日：2022-06-23

申请号：US17133065

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Souvik Ghosh ,  Willy Rachmady ,  Ashish Agrawal ,  Siddharth Chouksey ,  Jessica Torres ,  Jack Kavalieros ,  Matthew Metz ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/45 ,  H01L29/40 ,  H01L29/66 ,  H01L23/00 ,  H01L27/22 ,  H01L27/24

Abstract: An integrated circuit interconnect structure includes a metallization level above a first device level. The metallization level includes an interconnect structure coupled to the device structure, a conductive cap including an alloy of a metal of the interconnect structure and either silicon or germanium on an uppermost surface of the interconnect structure. A second device level above the conductive cap includes a transistor coupled with the conductive cap. The transistor includes a channel layer including a semiconductor material, where at least one sidewall of the conductive cap is co-planar with a sidewall of the channel layer. The transistor further includes a gate on a first portion of the channel layer, where the gate is between a source region and a drain region, where one of the source or the drain region is in contact with the conductive cap.

公开(公告)号：US20230299040A1

公开(公告)日：2023-09-21

申请号：US17699024

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Jay Prakash Gupta ,  Souvik Ghosh ,  Kimin Jun ,  Bhupendra Kumar ,  Shashi Vyas ,  Anup Pancholi

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/03 ,  H01L24/08 ,  H01L24/05 ,  H01L2224/0345 ,  H01L2224/03849 ,  H01L2224/08147 ,  H01L2224/05687 ,  H01L2224/05147 ,  H01L2224/05666 ,  H01L2224/05187 ,  H01L2224/8009 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80948 ,  H01L2924/35121

Abstract: A microelectronic assembly and a method of forming same. The assembly includes: first and second microelectronic structures; and an interface layer between the two microelectronic structures including dielectric portions in registration with dielectric layers of each of the microelectronic structures, and electrically conductive portions in registration with electrically conductive structures of each of the microelectronic structures, wherein the dielectric portions include an oxide of a metal, and the electrically conductive portions include the metal.