公开(公告)号：US11791327B2

公开(公告)日：2023-10-17

申请号：US17411635

申请日：2021-08-25

申请人： SANDISK TECHNOLOGIES LLC

发明人： Kwang-Ho Kim ,  Masaaki Higashitani ,  Fumiaki Toyama ,  Akio Nishida

IPC分类号： H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/48 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41

CPC分类号： H01L25/18 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L23/481 ,  H01L23/5226 ,  H01L2224/08145 ,  H01L2224/8083 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/10 ,  H10B41/27 ,  H10B41/41

摘要： A memory-containing die includes a three-dimensional memory array, a memory dielectric material layer located on a first side of the three-dimensional memory array, and memory-side bonding pads. A logic die includes a peripheral circuitry configured to control operation of the three-dimensional memory array, logic dielectric material layers located on a first side of the peripheral circuitry, and logic-side bonding pads included in the logic dielectric material layers. The logic-side bonding pads includes a pad-level mesh structure electrically connected to a source power supply circuit within the peripheral circuitry and containing an array of discrete openings therethrough, and discrete logic-side bonding pads. The logic-side bonding pads are bonded to a respective one, or a respective subset, of the memory-side bonding pads. The pad-level mesh structure can be used as a component of a source power distribution network.

公开(公告)号：US09922953B2

公开(公告)日：2018-03-20

申请号：US15121855

申请日：2015-02-26

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Paul Gondcharton ,  Lamine Benaissa ,  Bruno Imbert ,  Hubert Moriceau

IPC分类号： H01L21/00 ,  H01L21/47 ,  H01L21/44 ,  H01L23/00 ,  H01L21/18 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/83 ,  H01L21/185 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0381 ,  H01L2224/03845 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/2745 ,  H01L2224/2755 ,  H01L2224/27845 ,  H01L2224/29147 ,  H01L2224/80055 ,  H01L2224/80357 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/8092 ,  H01L2224/80948 ,  H01L2224/83895 ,  H01L2225/06524 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01008 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/00012

摘要： A method for producing a structure by direct bonding of two elements, the method including: production of the elements to be assembled and assembly of the elements. The production of the elements to be assembled includes: deposition on a substrate of a TiN layer by physical vapor deposition, and deposition of a copper layer on the TiN layer. The assembly of the elements includes: polishing the surfaces of the copper layers intended to come into contact so that they have a roughness of less than 1 nm RMS and hydrophilic properties, bringing the surfaces into contact, and storing the structure at atmospheric pressure and at ambient temperature.

公开(公告)号：US20160379958A1

公开(公告)日：2016-12-29

申请号：US15261402

申请日：2016-09-09

申请人： THRUCHIP JAPAN INC.

发明人： Tadahiro Kuroda

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/64 ,  H01L27/06 ,  H01L27/092 ,  H01L23/00 ,  H01L25/00 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/645 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/18 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/092 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80006 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/80986 ,  H01L2224/81005 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/9222 ,  H01L2224/92225 ,  H01L2224/92227 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/19107 ,  H01L2224/80 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/20752

摘要： The invention relates to a multilayer semiconductor integrated circuit device which is provided with a smaller space for a three-dimensional multilayer configuration at a lower cost and with a sufficient power supply quality. A first semiconductor integrated circuit device is provided with a first penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the first power supply potential, and a second penetrating semiconductor region that penetrates through the first semiconductor body in the thickness direction and that is connected to the second power supply potential. A second semiconductor integrated circuit device having a first electrode and a second electrode is layered on top of the first semiconductor integrated circuit device so that the first electrode and the second electrode are respectively connected to the first penetrating semiconductor region and the second penetrating semiconductor region.

摘要翻译： 本发明涉及一种多层半导体集成电路器件，其以较低的成本和足够的电源质量为三维多层结构提供较小的空间。 第一半导体集成电路器件设置有第一穿透半导体区域，该第一穿透半导体区域在厚度方向上穿过第一半导体本体并且连接到第一电源电位，以及穿过第一半导体本体的第二穿透半导体区域 厚度方向并连接到第二电源电位。 具有第一电极和第二电极的第二半导体集成电路器件层叠在第一半导体集成电路器件的顶部上，使得第一电极和第二电极分别连接到第一穿透半导体区域和第二穿透半导体区域。

公开(公告)号：US20150028493A1

公开(公告)日：2015-01-29

申请号：US14191308

申请日：2014-02-26

申请人： Kabushiki Kaisha Toshiba

发明人： Kenro NAKAMURA ,  Hirokazu EZAWA

IPC分类号： H01L23/00 ,  H01L23/522

CPC分类号： H01L23/535 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/80 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05026 ,  H01L2224/05547 ,  H01L2224/05557 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05686 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11616 ,  H01L2224/13009 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/80203 ,  H01L2224/8083 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04941

摘要： A method of manufacturing a semiconductor device includes forming an opening in a first substrate and filling the opening with a metal to form a first connection electrode. The first substrate is then polished by chemical mechanical polishing under conditions such that a polishing rate of the metal is less that of the region surrounding the metal. The chemical mechanical polishing thereby causes the first connection electrode to protrude from the surface of the first substrate. The first substrate is stacked with a second substrate having a second connection electrode. The first and second connection electrodes are bonded by applying pressure and heating to a temperature that is below the melting point of the metal of the first connection electrode.

摘要翻译： 一种制造半导体器件的方法包括在第一衬底中形成开口并用金属填充开口以形成第一连接电极。 然后通过化学机械抛光在使得金属的抛光速率小于金属周围区域的条件下抛光第一衬底。 化学机械抛光使第一连接电极从第一基板的表面突出。 第一衬底与具有第二连接电极的第二衬底层叠。 通过施加压力和加热将第一和第二连接电极接合到低于第一连接电极的金属的熔点的温度。

公开(公告)号：US08928119B2

公开(公告)日：2015-01-06

申请号：US12405240

申请日：2009-03-17

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： H01L23/48 ,  H01L21/762 ,  H01L23/538 ,  G11C5/02 ,  H01L21/768 ,  H01L27/06 ,  H01L27/108 ,  H01L25/065 ,  H01L23/522 ,  G11C5/06

CPC分类号： G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路减薄到厚度小于50μm，并将电路结合到电路堆栈，同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US20140346649A1

公开(公告)日：2014-11-27

申请号：US14457515

申请日：2014-08-12

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： H01L29/02

CPC分类号： G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路的薄型化至小于50微米的厚度，并且将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US08796862B2

公开(公告)日：2014-08-05

申请号：US13963164

申请日：2013-08-09

申请人： Glenn J Leedy

发明人： Glenn J Leedy

IPC分类号： H01L23/48

CPC分类号： G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 microns in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路的薄型化至小于50微米的厚度，并且将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US08003973B2

公开(公告)日：2011-08-23

申请号：US12855184

申请日：2010-08-12

申请人： Thaddeus John Gabara

发明人： Thaddeus John Gabara

IPC分类号： H01L29/06

CPC分类号： H01L21/6833 ,  H01L23/645 ,  H01L24/12 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/11526 ,  H01L2223/6677 ,  H01L2224/13021 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8083 ,  H01L2224/81143 ,  H01L2224/81801 ,  H01L2224/8183 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/95145 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/203 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02252 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/0002

摘要： A multi layered substrate structure can be formed where the substrates are coupled together using surface Coulomb forces. Connect substrates electrically connects signals and DC voltages between the substrates. The connect substrates bypass output/input buffers between two communicating substrates. The capacitor substrates provide a fully charged capacitor that provides additional energy to a levitated substrate if the capacitor substrate is connected to the levitated substrate. VLSI systems can also be build on each of the substrates.

摘要翻译： 可以形成多层基板结构，其中基板使用表面库仑力联接在一起。 连接基板在基板之间电连接信号和直流电压。 连接基板在两个通信基板之间旁路输出/输入缓冲器。 电容器基板提供完全充电的电容器，如果电容器基板连接到悬浮基板，则向悬浮基板提供额外的能量。 VLSI系统也可以构建在每个基板上。

公开(公告)号：US20090219744A1

公开(公告)日：2009-09-03

申请号：US12405241

申请日：2009-03-17

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/00

CPC分类号： G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

公开(公告)号：US20090219742A1

公开(公告)日：2009-09-03

申请号：US12405235

申请日：2009-03-17

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： G11C5/02 ,  G11C29/00 ,  H01L29/00

CPC分类号： G11C5/02 ,  G11C5/06 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L27/0688 ,  H01L27/10897 ,  H01L29/02 ,  H01L2224/8083 ,  H01L2224/8384 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路薄化到小于50um的厚度，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。