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公开(公告)号:US20240304576A1
公开(公告)日:2024-09-12
申请号:US18586366
申请日:2024-02-23
申请人: Kioxia Corporation
发明人: Yuya KIYOMURA , Ayako KAWANISHI , Yuta TAGUCHI , Ayumi WATARAI , Ippei KUME
CPC分类号: H01L24/05 , H01L24/03 , H01L24/08 , H01L25/18 , H10B80/00 , H01L2224/03848 , H01L2224/05009 , H01L2224/05017 , H01L2224/05018 , H01L2224/05073 , H01L2224/05082 , H01L2224/05087 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05557 , H01L2224/05558 , H01L2224/05647 , H01L2224/08145 , H01L2924/1438
摘要: A memory device includes a first chip including a first electrode and a second chip including a second electrode. The first electrode includes a first conductive film having a first surface in contact with the second electrode at a boundary region of the first and second electrodes, a second surface spaced apart from the boundary region, and a third surface between the first surface and the second surface, and having a first portion on the first surface side and a second portion on the second surface side, and includes a second conductive film covering the second surface and the third surface of the first conductive film. A (111) orientation ratio of copper contained in the first portion is higher than a (111) orientation ratio of copper contained in the second portion.
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公开(公告)号:US20240047389A1
公开(公告)日:2024-02-08
申请号:US18141675
申请日:2023-05-01
发明人: Hyeonmin Lee , Jihoon Kim , Aenee Jang
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L24/05 , H01L24/80 , H01L24/94 , H01L24/96 , H01L25/0657 , H01L24/08 , H01L24/06 , H01L2924/1431 , H01L2224/94 , H01L2224/96 , H01L2224/95001 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1434 , H01L2225/06527 , H01L2225/06541 , H01L2224/80203 , H01L2224/08145 , H01L2224/0603 , H01L2224/06051 , H01L2224/06133 , H01L2224/05007 , H01L2224/05187 , H01L2224/05124 , H01L2224/05647 , H01L2224/05015 , H01L2224/05018 , H01L2224/05082 , H01L2224/05541 , H01L2224/05555 , H01L2224/05558 , H01L2224/05687
摘要: A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.
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公开(公告)号:US11848346B2
公开(公告)日:2023-12-19
申请号:US17162221
申请日:2021-01-29
发明人: Satoru Wakiyama , Kan Shimizu , Toshihiko Hayashi , Takuya Nakamura , Naoki Jyo
IPC分类号: H01L23/00 , H01L27/146 , H01L23/31
CPC分类号: H01L27/14636 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/81 , H01L27/14607 , H01L27/14634 , H01L27/14643 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/0239 , H01L2224/039 , H01L2224/0345 , H01L2224/0346 , H01L2224/0361 , H01L2224/0391 , H01L2224/03616 , H01L2224/03828 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05082 , H01L2224/05157 , H01L2224/05181 , H01L2224/05187 , H01L2224/05547 , H01L2224/05548 , H01L2224/05571 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05669 , H01L2224/0603 , H01L2224/06181 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/16145 , H01L2224/16146 , H01L2224/48463 , H01L2224/73257 , H01L2224/81011 , H01L2224/8114 , H01L2224/81022 , H01L2224/81065 , H01L2224/8182 , H01L2224/81191 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81469 , H01L2924/00014 , H01L2224/05647 , H01L2924/00014 , H01L2224/05655 , H01L2924/00014 , H01L2224/05664 , H01L2924/00014 , H01L2224/05644 , H01L2924/00014 , H01L2224/05669 , H01L2924/00014 , H01L2224/05157 , H01L2924/00014 , H01L2224/05187 , H01L2924/04941 , H01L2224/05181 , H01L2924/00014 , H01L2224/05187 , H01L2924/04953 , H01L2224/131 , H01L2924/014 , H01L2224/13111 , H01L2924/01047 , H01L2224/13111 , H01L2924/01083 , H01L2224/13111 , H01L2924/01029 , H01L2224/13111 , H01L2924/01049 , H01L2224/13111 , H01L2924/01047 , H01L2924/01029 , H01L2224/0345 , H01L2924/00014 , H01L2224/0346 , H01L2924/00014 , H01L2224/03616 , H01L2924/00014 , H01L2224/0361 , H01L2924/00012 , H01L2224/81447 , H01L2924/00014 , H01L2224/81455 , H01L2924/00014 , H01L2224/81464 , H01L2924/00014 , H01L2224/81444 , H01L2924/00014 , H01L2224/81469 , H01L2924/00014 , H01L2224/039 , H01L2224/0345 , H01L2224/0346 , H01L2224/03616 , H01L2224/0361 , H01L2224/48463 , H01L2924/00014 , H01L2224/05571 , H01L2924/00012 , H01L2224/0239 , H01L2924/01029 , H01L2924/00014 , H01L2224/45099
摘要: An imaging device includes a first semiconductor element including at least one bump pad that has a concave shape. The at least one bump pad includes a first metal layer and a second metal layer on the first metal layer. The imaging device includes a second semiconductor element including at least one electrode. The imaging device includes a microbump electrically connecting the at least one bump pad to the at least one electrode. The microbump includes a diffused portion of the second metal layer, and first semiconductor element or the second semiconductor element includes a pixel unit.
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公开(公告)号:US11728296B2
公开(公告)日:2023-08-15
申请号:US17073533
申请日:2020-10-19
发明人: Hsiao Yun Lo , Lin-Chih Huang , Tasi-Jung Wu , Hsin-Yu Chen , Yung-Chi Lin , Ku-Feng Yang , Tsang-Jiuh Wu , Wen-Chih Chiou
CPC分类号: H01L24/05 , H01L23/481 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/0346 , H01L2224/0391 , H01L2224/03462 , H01L2224/03602 , H01L2224/03614 , H01L2224/03616 , H01L2224/0401 , H01L2224/05008 , H01L2224/05012 , H01L2224/05017 , H01L2224/05025 , H01L2224/05026 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05139 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05187 , H01L2224/05565 , H01L2224/05571 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05655 , H01L2224/05684 , H01L2224/1145 , H01L2224/11334 , H01L2224/11462 , H01L2224/131 , H01L2224/13023 , H01L2224/13026 , H01L2224/13111 , H01L2224/13147 , H01L2924/00012 , H01L2924/00014 , H01L2924/013 , H01L2924/01029 , H01L2924/01047 , H01L2924/13091 , H01L2924/00014 , H01L2224/05187 , H01L2924/04941 , H01L2224/05187 , H01L2924/04953 , H01L2224/0345 , H01L2924/00014 , H01L2224/05181 , H01L2924/00014 , H01L2224/05124 , H01L2924/00014 , H01L2224/05184 , H01L2924/00014 , H01L2224/05139 , H01L2924/00014 , H01L2224/05647 , H01L2924/013 , H01L2224/05624 , H01L2924/00014 , H01L2224/05684 , H01L2924/00014 , H01L2224/05639 , H01L2924/00014 , H01L2224/03602 , H01L2924/00014 , H01L2224/03614 , H01L2924/00014 , H01L2224/13111 , H01L2924/01047 , H01L2924/01029 , H01L2224/13147 , H01L2924/00014 , H01L2224/1145 , H01L2924/00014 , H01L2224/11462 , H01L2924/00014 , H01L2224/131 , H01L2924/014
摘要: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.
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公开(公告)号:US20230209926A1
公开(公告)日:2023-06-29
申请号:US17951977
申请日:2022-09-23
发明人: Shinhyuk Yang , Donghan Kang , Yujin Kim , Jeehoon Kim , Junki Lee
CPC分类号: H01L27/3276 , H01L24/05 , H01L51/56 , H01L2227/323 , H01L2224/0345 , H01L2224/03614 , H01L2224/0381 , H01L2224/05573 , H01L2224/05016 , H01L2224/05027 , H01L2224/05083 , H01L2224/05187 , H01L2224/05188 , H01L2224/05166 , H01L2224/0518 , H01L2224/05184 , H01L2224/05147 , H01L2224/05557 , H01L2224/05686 , H01L2924/0549 , H01L2224/05571 , H01L2224/05562 , H01L2924/0542 , H01L2924/0543
摘要: A display apparatus is disclosed that includes a substrate, a display element, a transistor, and a pad. The substrate includes a display area and a peripheral area. The display element is disposed on the display area. The transistor is electrically connected to the display element. The pad is disposed on the peripheral area and having a multilayered structure. The pad includes a pad metal layer, a first pad protective layer disposed on the pad metal layer, and a second pad protective layer interposed between the pad metal layer and the first pad protective layer. The second pad protective layer includes a different material from the first pad protective layer. The transistor includes a semiconductor layer disposed on the substrate, a gate electrode disposed on a gate insulating layer that covers the semiconductor layer, and a connection electrode arranged on an interlayer insulating layer covering the gate electrode. The connection electrode has the same multilayered structure as the multilayered structure of the pad, and the connection electrode is connected to the semiconductor layer.
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公开(公告)号:US09911708B2
公开(公告)日:2018-03-06
申请号:US15403797
申请日:2017-01-11
CPC分类号: H01L24/13 , H01L24/03 , H01L24/11 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/0401 , H01L2224/05 , H01L2224/05166 , H01L2224/05187 , H01L2224/05647 , H01L2224/10126 , H01L2224/11001 , H01L2224/11462 , H01L2224/1147 , H01L2224/13011 , H01L2224/13019 , H01L2224/13026 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13111 , H01L2224/13147 , H01L2224/13155 , H01L2224/16227 , H01L2224/16238 , H01L2224/81141 , H01L2224/81143 , H01L2224/81815 , H01L2924/01029 , H01L2924/381 , H01L2924/00014 , H01L2924/04941 , H01L2924/0496 , H01L2924/01074 , H01L2924/01024 , H01L2924/00012 , H01L2924/014 , H01L2924/01027
摘要: A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is formed on a first conductive layer to define a conductive pillar that includes a non-planar top surface defining a recess aligned with the hollow core.
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公开(公告)号:US09831170B2
公开(公告)日:2017-11-28
申请号:US15354447
申请日:2016-11-17
IPC分类号: H01L23/498 , H01L21/48 , H01L21/56 , H01L21/66 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/552
CPC分类号: H01L23/49838 , H01L21/304 , H01L21/4853 , H01L21/4857 , H01L21/4867 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/78 , H01L22/14 , H01L22/34 , H01L23/3114 , H01L23/3128 , H01L23/3164 , H01L23/48 , H01L23/49822 , H01L23/49894 , H01L23/552 , H01L23/562 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L2224/0231 , H01L2224/02311 , H01L2224/02313 , H01L2224/02331 , H01L2224/02377 , H01L2224/0239 , H01L2224/03 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0401 , H01L2224/04105 , H01L2224/05008 , H01L2224/05024 , H01L2224/05083 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05171 , H01L2224/05187 , H01L2224/05548 , H01L2224/05568 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/0558 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/05669 , H01L2224/05671 , H01L2224/05687 , H01L2224/0569 , H01L2224/08225 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13294 , H01L2224/133 , H01L2224/16227 , H01L2224/19 , H01L2224/2101 , H01L2224/214 , H01L2224/215 , H01L2224/24137 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/80904 , H01L2224/81 , H01L2224/81395 , H01L2224/81444 , H01L2224/81447 , H01L2224/81815 , H01L2224/81856 , H01L2224/81874 , H01L2224/8385 , H01L2224/92 , H01L2224/92244 , H01L2224/94 , H01L2224/95001 , H01L2224/96 , H01L2224/97 , H01L2924/00 , H01L2924/00014 , H01L2924/01322 , H01L2924/0635 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/15313 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/351 , H01L2924/3511 , H01L2224/11 , H01L2924/01029 , H01L2924/014 , H01L2924/01028 , H01L2924/0105 , H01L2924/01082 , H01L2924/01074 , H01L2924/01023 , H01L2924/01013 , H01L2924/01079 , H01L2924/01047 , H01L2924/04941 , H01L2924/0665
摘要: A semiconductor module can comprise a fully molded base portion comprising a planar surface that further comprises a semiconductor die comprising contact pads, conductive pillars coupled to the contact pads and extending to the planar surface, and an encapsulant material disposed over the active surface, four side surfaces, and around the conductive pillars, wherein ends of the conductive pillars are exposed from the encapsulant material at the planar surface of the fully molded base portion. A build-up interconnect structure comprising a routing layer can be disposed over the fully molded base portion. A photo-imageable solder mask material can be disposed over the routing layer and comprise openings to form surface mount device (SMD) land pads electrically coupled to the semiconductor die and the conductive pillars. A SMD component can be electrically coupled to the SMD land pads with surface mount technology (SMT).
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公开(公告)号:US09768120B2
公开(公告)日:2017-09-19
申请号:US13683393
申请日:2012-11-21
发明人: Philipp Seng , Khalil Hosseini , Anton Mauder
IPC分类号: H01L23/538 , H01L21/78 , H01L29/06 , H01L23/00 , H01L23/373 , H01L23/495
CPC分类号: H01L23/538 , H01L21/78 , H01L23/3735 , H01L23/49513 , H01L24/03 , H01L24/05 , H01L24/29 , H01L24/32 , H01L24/83 , H01L24/94 , H01L29/0657 , H01L2224/03001 , H01L2224/03462 , H01L2224/0347 , H01L2224/04026 , H01L2224/05018 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05169 , H01L2224/05172 , H01L2224/05184 , H01L2224/05187 , H01L2224/05558 , H01L2224/05564 , H01L2224/05582 , H01L2224/05639 , H01L2224/05644 , H01L2224/26145 , H01L2224/291 , H01L2224/29116 , H01L2224/2912 , H01L2224/32058 , H01L2224/32225 , H01L2224/32245 , H01L2224/83365 , H01L2224/83455 , H01L2224/83815 , H01L2224/83825 , H01L2224/94 , H01L2924/00014 , H01L2924/10157 , H01L2924/10158 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/15747 , H01L2924/014 , H01L2924/01023 , H01L2924/0105 , H01L2924/01047 , H01L2924/047 , H01L2224/03 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要: A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced.
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公开(公告)号:US09748135B2
公开(公告)日:2017-08-29
申请号:US14828608
申请日:2015-08-18
发明人: Yuri M. Brovman , Brian M. Erwin , Nicholas A. Polomoff , Jennifer D. Schuler , Matthew E. Souter , Christopher L. Tessler
IPC分类号: H01L21/768
CPC分类号: H01L21/76841 , H01L21/76825 , H01L21/76837 , H01L21/7684 , H01L21/76849 , H01L21/7685 , H01L21/76852 , H01L21/76865 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03614 , H01L2224/03632 , H01L2224/0381 , H01L2224/039 , H01L2224/0401 , H01L2224/05187 , H01L2224/05647 , H01L2224/1182 , H01L2224/13007 , H01L2224/13147 , H01L2224/13562 , H01L2224/13687 , H01L2924/00014 , H01L2924/04953 , H01L2924/04941 , H01L2924/00012
摘要: A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.
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公开(公告)号:US20170186725A1
公开(公告)日:2017-06-29
申请号:US15331957
申请日:2016-10-24
发明人: Yuichi OTA , Kentaro KITA , Takehiro OURA , Kohei YOSHIDA
IPC分类号: H01L23/00 , H01L21/78 , H01L21/8238 , H01L21/304 , H01L23/544 , H01L21/683
CPC分类号: H01L24/94 , H01L21/304 , H01L21/6836 , H01L21/78 , H01L21/823814 , H01L21/823871 , H01L21/823892 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/92 , H01L2221/68327 , H01L2221/6834 , H01L2221/68386 , H01L2223/5446 , H01L2224/0218 , H01L2224/0219 , H01L2224/02206 , H01L2224/02215 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0348 , H01L2224/03828 , H01L2224/0391 , H01L2224/03914 , H01L2224/0401 , H01L2224/05018 , H01L2224/05019 , H01L2224/05022 , H01L2224/05082 , H01L2224/05084 , H01L2224/05147 , H01L2224/05155 , H01L2224/05187 , H01L2224/05562 , H01L2224/05644 , H01L2224/1132 , H01L2224/11334 , H01L2224/1146 , H01L2224/11464 , H01L2224/1181 , H01L2224/11849 , H01L2224/119 , H01L2224/13026 , H01L2224/131 , H01L2224/13294 , H01L2224/133 , H01L2224/92 , H01L2224/94 , H01L2924/04941 , H01L2924/07025 , H01L2224/11 , H01L2924/00014 , H01L2924/014 , H01L2221/68304
摘要: A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering multiple bonding pads, a first protective film over the insulating film, and a second protective film over the first protective film. In semiconductor chips, multiple electrode layers are coupled electrically to each of the bonding pads via first openings formed in the insulating film and second openings formed in the first protective film. Multiple bump electrodes are coupled electrically to each of the electrode layers via third openings formed in the second protective film. In pseudo chips, the second openings are formed in the first protective film and the third openings are formed in the second protective film. The insulating film is exposed at the bottom of the second openings coinciding with the third openings. A protective tape is applied to a principal plane to cover the bump electrodes.
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