公开(公告)号：US20190393606A1

公开(公告)日：2019-12-26

申请号：US16017093

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Sri Chaitra CHAVALI ,  Siddharth ALUR ,  Sheng LI

IPC: H01Q9/04 ,  H01Q5/35 ,  H01L23/66

Abstract: Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

公开(公告)号：US20220230965A1

公开(公告)日：2022-07-21

申请号：US17716955

申请日：2022-04-08

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Islam A. SALAMA ,  Sri Ranga Sai BOYAPATI ,  Sheng LI ,  Kristof DARMAWIKARTA ,  Robert L. SANKMAN ,  Amruthavalli Pallavi ALUR

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20240332203A1

公开(公告)日：2024-10-03

申请号：US18740068

申请日：2024-06-11

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Islam A. SALAMA ,  Sri Ranga Sai BOYAPATI ,  Sheng LI ,  Kristof DARMAWIKARTA ,  Robert L. SANKMAN ,  Amruthavalli Pallavi ALUR

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L25/11

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/25 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/112 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/22 ,  H01L2224/224 ,  H01L2224/24226 ,  H01L2224/73103 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2924/15311

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

公开(公告)号：US20220108957A1

公开(公告)日：2022-04-07

申请号：US17555222

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Robert Alan MAY ,  Islam A. SALAMA ,  Sri Ranga Sai BOYAPATI ,  Sheng LI ,  Kristof DARMAWIKARTA ,  Robert L. SANKMAN ,  Amruthavalli Pallavi ALUR

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.