公开(公告)号：US20190096452A1

公开(公告)日：2019-03-28

申请号：US15926837

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G11C7/10 ,  G06F13/16 ,  G06F9/4401 ,  G11C14/00 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US10515674B2

公开(公告)日：2019-12-24

申请号：US15926837

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G06F12/00 ,  G11C7/10 ,  G06F13/16 ,  G06F9/4401 ,  G11C14/00 ,  G06F12/10 ,  G06F13/00 ,  G06F13/28

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US09922689B2

公开(公告)日：2018-03-20

申请号：US15089370

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G06F13/00 ,  G06F13/28 ,  G11C7/10 ,  G06F9/44 ,  G11C14/00 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.

公开(公告)号：US20170287532A1

公开(公告)日：2017-10-05

申请号：US15089370

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Robert A. Branch ,  Murugasamy K. Nachimuthu ,  Sundar Muthusamy

IPC: G11C7/10 ,  G11C14/00 ,  G06F9/44

CPC classification number: G11C7/1072 ,  G06F9/4401 ,  G06F12/10 ,  G06F13/16 ,  G06F13/1694 ,  G06F2212/1044 ,  G11C14/0063 ,  G11C14/0081 ,  G11C14/009

Abstract: Technology for a system is described. The system can include one or more processors. The system can include a memory associated with the one or more processors. The system can include a memory controller comprising logic to create a reserved memory region in a system physical address (SPA) map. The memory controller can comprise logic to detect when the one or more processors are brought online. The memory controller can comprise logic to map the memory associated with the one or more processors that are brought online to the reserved memory region in the SPA map.