公开(公告)号：US20200027500A1

公开(公告)日：2020-01-23

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  Wei P. CHEN ,  Suresh CHITTOR ,  George VERGIS

IPC: G11C11/406 ,  G06F13/16 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

公开(公告)号：US20200019513A1

公开(公告)日：2020-01-16

申请号：US16584612

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Vivek KOZHIKKOTTU ,  Suresh CHITTOR ,  Esha CHOUKSE ,  Shankar Ganesh RAMASUBRAMANIAN

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/02 ,  G06F11/30 ,  G06F13/16

Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.