公开(公告)号：US20220392519A1

公开(公告)日：2022-12-08

申请号：US17892000

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Randy B. OSBORNE ,  Christopher P. MOZAK ,  Shankar Ganesh RAMASUBRAMANIAN

IPC: G11C11/4093 ,  H01L25/065 ,  G11C11/4096 ,  G11C5/06

Abstract: Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.

公开(公告)号：US20200019513A1

公开(公告)日：2020-01-16

申请号：US16584612

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Vivek KOZHIKKOTTU ,  Suresh CHITTOR ,  Esha CHOUKSE ,  Shankar Ganesh RAMASUBRAMANIAN

IPC: G06F12/1045 ,  G06F12/06 ,  G06F12/02 ,  G06F11/30 ,  G06F13/16

Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.