公开(公告)号：US20240222347A1

公开(公告)日：2024-07-04

申请号：US18148338

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Kuljit S. Bains ,  Wilfred Gomes ,  Don Douglas Josephson ,  Surhud V. Khare ,  Christopher Philip Mozak ,  Randy B. Osborne ,  Pushkar Ranade ,  Abhishek Anil Sharma

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L24/16 ,  H10B80/00 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).

公开(公告)号：US20200313722A1

公开(公告)日：2020-10-01

申请号：US16903354

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： James Alexander McCall ,  Yunhui Chu ,  Christopher Philip Mozak ,  Derek M. Conrow ,  Christian Karl

IPC: H04B3/32 ,  H04B3/487

Abstract: An apparatus comprises a first data line coupled to a first driver; a second data line coupled to a second driver; and a crosstalk cancelation circuit comprising a third driver coupled between the first data line and the second data line, the crosstalk cancelation circuit to compensate for far end crosstalk introduced from the first data line to the second data line.