公开(公告)号：US20250156366A1

公开(公告)日：2025-05-15

申请号：US18657823

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Cong ZHANG ,  Tao ZHAO ,  Yi Liu ,  Jian WANG ,  Fan WANG ,  Zhonghua SUN ,  Xin ZHANG ,  Di ZHANG

IPC: G06F13/42 ,  G06F13/40

Abstract: A method and system for optimizing overall throughput of a Peripheral Component Interconnect Express (PCIe)/Compute Express Link (CXL) host bridge. The PCIe/CXL host bridge includes a plurality of ports, and one or more devices are connected to the ports. Credits are initially allocated to the ports of the PCIe/CXL host bridge. A link status on the ports of the PCIe/CXL host bridge and/or a status of scheduled workloads on a host are then determined. The credits allocated to the ports of the PCIe/CXL host bridge are adjusted based on the link status and/or the status of scheduled workloads. A PCIe driver may detect the link status of each port of the PCIe/CXL host bridge and request to adjust the credits based on the link status. An orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.

公开(公告)号：US20240296110A1

公开(公告)日：2024-09-05

申请号：US18572201

申请日：2021-09-29

Applicant: Intel Corporation

Inventor： Tao ZHAO ,  Yun LIU ,  Edwin Lei WANG

IPC: G06F11/36

CPC classification number: G06F11/3688 ,  G06F11/3664

Abstract: Examples relate to an apparatus, device, method, and computer program for performing unit tests on firmware code, and to an apparatus, device, method, and computer program for preparing data for performing unit tests on firmware code. The firmware code is suitable for interacting with a hardware device. The apparatus comprises circuitry configured to obtain a timeline of changes of transaction data encountered at one or more interfaces of the hardware device during simulation of the hardware device, the simulation being based on one or more simulation parameters defined by one or more unit tests to be performed on the firmware code. The circuitry is configured to perform the one or more unit tests of the firmware code using the timeline of changes of transaction data of the simulated hardware device, the one or more unit tests being based on the one or more simulation parameters.