公开(公告)号：US20240291527A1

公开(公告)日：2024-08-29

申请号：US18562844

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Xin ZHANG ,  Di LIU

IPC: H04B7/0452 ,  H04B7/06

CPC classification number: H04B7/0452 ,  H04B7/063 ,  H04B7/0632 ,  H04B7/0639

Abstract: Processing circuitry for a communication station configured to facilitate multi-user multiple-input multiple output (MU-MIMO) service. The processing circuitry can perform a multi-user selection for data transmission on a shared radio resource from a plurality of User Equipments (UEs). The processing circuitry selects one or more of the plurality of candidate UEs in time domain based on time-domain scheduling algorithm, obtain historical throughput data and input for each selected UE. The input includes a channel state indicator including a single-user channel quality indicator (SU-CQI), a precoding matrix indicator (PMI), rank indicator, and a channel state matrix. A trained reinforcement learning agent (RL agent) using the obtained input infers a rating score for each of the plurality of UEs. The processing circuitry schedules the one or more the UEs for transmission respectively on the plurality of radio resources based on the plurality of score ratings and allocate the plurality of radio resources.

公开(公告)号：US20250156366A1

公开(公告)日：2025-05-15

申请号：US18657823

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Cong ZHANG ,  Tao ZHAO ,  Yi Liu ,  Jian WANG ,  Fan WANG ,  Zhonghua SUN ,  Xin ZHANG ,  Di ZHANG

IPC: G06F13/42 ,  G06F13/40

Abstract: A method and system for optimizing overall throughput of a Peripheral Component Interconnect Express (PCIe)/Compute Express Link (CXL) host bridge. The PCIe/CXL host bridge includes a plurality of ports, and one or more devices are connected to the ports. Credits are initially allocated to the ports of the PCIe/CXL host bridge. A link status on the ports of the PCIe/CXL host bridge and/or a status of scheduled workloads on a host are then determined. The credits allocated to the ports of the PCIe/CXL host bridge are adjusted based on the link status and/or the status of scheduled workloads. A PCIe driver may detect the link status of each port of the PCIe/CXL host bridge and request to adjust the credits based on the link status. An orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.