公开(公告)号：US20240403166A1

公开(公告)日：2024-12-05

申请号：US18735239

申请日：2024-06-06

Applicant: Intel Corporation

Inventor： Zhonghua SUN ,  Pei GAO ,  Yue LIU ,  Liangqi ZHU ,  Yue YAO ,  Junyu TONG ,  Hua MA ,  Cong ZHANG

IPC: G06F11/10 ,  G06F11/07

Abstract: Provided is a method comprising obtaining information about a detected memory error in a memory device, the memory device being connected to a first host via a compute express link, CXL, interface. The method comprises further recording the memory error information into a firmware of the memory device.

公开(公告)号：US20250156366A1

公开(公告)日：2025-05-15

申请号：US18657823

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Cong ZHANG ,  Tao ZHAO ,  Yi Liu ,  Jian WANG ,  Fan WANG ,  Zhonghua SUN ,  Xin ZHANG ,  Di ZHANG

IPC: G06F13/42 ,  G06F13/40

Abstract: A method and system for optimizing overall throughput of a Peripheral Component Interconnect Express (PCIe)/Compute Express Link (CXL) host bridge. The PCIe/CXL host bridge includes a plurality of ports, and one or more devices are connected to the ports. Credits are initially allocated to the ports of the PCIe/CXL host bridge. A link status on the ports of the PCIe/CXL host bridge and/or a status of scheduled workloads on a host are then determined. The credits allocated to the ports of the PCIe/CXL host bridge are adjusted based on the link status and/or the status of scheduled workloads. A PCIe driver may detect the link status of each port of the PCIe/CXL host bridge and request to adjust the credits based on the link status. An orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.

公开(公告)号：US20240289286A1

公开(公告)日：2024-08-29

申请号：US18572199

申请日：2021-09-26

Applicant: Intel Corporation

Inventor： Zhonghua SUN ,  Changcheng LIU ,  Yi SUN ,  Cong ZHANG ,  Di ZHANG ,  Zhuangzhi LI

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/404

Abstract: Examples relate to a concept for providing access to remote memory. A network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. The circuitry is configured to translate the memory transaction request to a cache transaction request. The circuitry is configured to provide the cache transaction request to the first host. The circuitry is configured to obtain a response to the cache transaction request from the first host. The circuitry is configured to provide information on the response to the cache transaction request to the second host.