公开(公告)号：US20250156366A1

公开(公告)日：2025-05-15

申请号：US18657823

申请日：2024-05-08

Applicant: Intel Corporation

Inventor： Cong ZHANG ,  Tao ZHAO ,  Yi Liu ,  Jian WANG ,  Fan WANG ,  Zhonghua SUN ,  Xin ZHANG ,  Di ZHANG

IPC: G06F13/42 ,  G06F13/40

Abstract: A method and system for optimizing overall throughput of a Peripheral Component Interconnect Express (PCIe)/Compute Express Link (CXL) host bridge. The PCIe/CXL host bridge includes a plurality of ports, and one or more devices are connected to the ports. Credits are initially allocated to the ports of the PCIe/CXL host bridge. A link status on the ports of the PCIe/CXL host bridge and/or a status of scheduled workloads on a host are then determined. The credits allocated to the ports of the PCIe/CXL host bridge are adjusted based on the link status and/or the status of scheduled workloads. A PCIe driver may detect the link status of each port of the PCIe/CXL host bridge and request to adjust the credits based on the link status. An orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.

公开(公告)号：US20220019444A1

公开(公告)日：2022-01-20

申请号：US17449098

申请日：2021-09-28

Applicant: Intel Corporation

Inventor： Di ZHANG ,  Sarathy JAYAKUMAR ,  Vincent ZIMMER ,  Fei LI ,  Bo HE ,  Zhuangzhi LI ,  Zhi JIN ,  Lin CHEN ,  Guomin JIANG

IPC: G06F9/4401 ,  G06F1/24

Abstract: An electronic device is disclosed, including a first set of processor cores including at least one processor core and a second set of processor cores including at least one processor core. The electronic device is configured such that during initialization of the electronic device: the first set of processor cores executes first initialization instructions in a first execution environment, the second set of processor cores executes second initialization instructions in a second execution environment, and the first set and the second set at least one of read or write to a shared register.

公开(公告)号：US20210225096A1

公开(公告)日：2021-07-22

申请号：US17055544

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Yao Zu DONG ,  Shuo LIU ,  Di ZHANG

IPC: G07C5/08 ,  G06F9/455 ,  G06F9/4401

Abstract: Apparatuses, methods and storage medium associated with in-vehicle computing, are disclosed herein. In embodiments, an in-vehicle system computing platform having a hypervisor to host one or more virtual machines (VMs) includes a memory shrink manager, and a memory snapshot manager. The memory shrink manager is configured to orchestrate shrinking a memory footprint of one of the one or more VMs for a suspend process invoked in response to the computing platform being powered off. The memory snapshot manager is configured to save the shrunken memory footprint of the one VM to the persistent storage during the suspend process, and to reload a subset of the saved shrunken memory footprint during a resume process to resume the one VM from suspension to the persistent storage. The resume process is invoked in response to the computing platform being powered on, cold booted.

公开(公告)号：US20240289286A1

公开(公告)日：2024-08-29

申请号：US18572199

申请日：2021-09-26

Applicant: Intel Corporation

Inventor： Zhonghua SUN ,  Changcheng LIU ,  Yi SUN ,  Cong ZHANG ,  Di ZHANG ,  Zhuangzhi LI

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F13/404

Abstract: Examples relate to a concept for providing access to remote memory. A network interface controller apparatus comprises circuitry configured to obtain a memory transaction request with respect to memory of a first host hosting the network interface controller apparatus from a second host. The circuitry is configured to translate the memory transaction request to a cache transaction request. The circuitry is configured to provide the cache transaction request to the first host. The circuitry is configured to obtain a response to the cache transaction request from the first host. The circuitry is configured to provide information on the response to the cache transaction request to the second host.