公开(公告)号：US20190212704A1

公开(公告)日：2019-07-11

申请号：US16242953

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Tarun MAHAJAN ,  Dheeraj SHETTY ,  Ramnarayanan MUTHUKARUPPAN

IPC: G04F10/00 ,  G06F1/06 ,  G05F1/56

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.

公开(公告)号：US20180267480A1

公开(公告)日：2018-09-20

申请号：US15462732

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Tarun MAHAJAN ,  Dheeraj SHETTY ,  Ramnarayanan MUTHUKARUPPAN

IPC: G04F10/00 ,  G05F1/56 ,  G06F1/06

CPC classification number: G04F10/005 ,  G05F1/561 ,  G06F1/06 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233

Abstract: An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a plurality of delay cells, wherein the delay line is coupled to the first and second clock lines, wherein the first clock is to sample the second clock; and circuitry coupled to the delay line, wherein the circuitry is to determine first or latest edge transitions from the outputs of the plurality of delay cells.