公开(公告)号：US20170205772A1

公开(公告)日：2017-07-20

申请号：US15370796

申请日：2016-12-06

Applicant: Marvell World Trade Ltd.

Inventor： Olivier BURG ,  Haisong WANG ,  Xiang GAO

IPC: G04F10/00

CPC classification number: G04F10/005 ,  H03B21/02 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/50 ,  H03M7/3004 ,  H03M2201/4233 ,  H04M1/505

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

公开(公告)号：US4010422A

公开(公告)日：1977-03-01

申请号：US409425

申请日：1973-10-25

Applicant: Kornelis Jan Wouda

Inventor： Kornelis Jan Wouda

IPC: H03M1/00 ,  H04B14/04 ,  H04B1/04

CPC classification number: H04B14/04 ,  H03M1/00 ,  H04B14/048 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2344 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/425 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.

公开(公告)号：US09401726B2

公开(公告)日：2016-07-26

申请号：US14554790

申请日：2014-11-26

Applicant: Silicon Laboratories Inc.

Inventor： Kareem A. Ragab ,  John Khoury

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M1/1023 ,  H03M1/00 ,  H03M1/0626 ,  H03M1/0695 ,  H03M1/1004 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/124 ,  H03M2201/4233

Abstract: A robust and fast background calibration technique for correction of time-interleaved ADC offset, gain, bandwidth, and timing mismatches is proposed. The technique combines the use of a calibration signal and a reference ADC. The calibration signal enhances robustness and makes the technique independent of the input signal's statistics. The reference ADC speeds up convergence and enables the use of a small amplitude calibration signal that does not significantly reduce the input signal dynamic range. The calibration signal can be subtracted or filtered from the ADC output and is therefore invisible to the ADC user.

Abstract translation: 提出了用于校正时间交织的ADC偏移，增益，带宽和时序不匹配的鲁棒且快速的背景校准技术。 该技术结合使用校准信号和参考ADC。 校准信号增强了鲁棒性，使得该技术独立于输入信号的统计。 参考ADC可以加快收敛速度​​，并且可以使用不会显着降低输入信号动态范围的小幅度校准信号。 校准信号可以从ADC输出中减去或滤波，因此ADC用户不可见。

公开(公告)号：US09166608B1

公开(公告)日：2015-10-20

申请号：US14731471

申请日：2015-06-05

Applicant: IMEC VZW

Inventor： Kazuaki Deguchi ,  Bob Verbruggen ,  Jan Craninckx

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/00 ,  H03M1/46 ,  H03M1/12

CPC classification number: H03M1/0604 ,  H03M1/00 ,  H03M1/002 ,  H03M1/1071 ,  H03M1/109 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/14 ,  H03M1/468 ,  H03M2201/4233

Abstract: Methods and devices herein relate to a method for estimating bandwidth mismatch in a time-interleaved A/D converter. An example method includes precharging terminals of capacitors to a first state in each channel of a plurality of channels and sampling a reference analog input voltage signal (Vref) applied via a first switchable path whereby the sampled input voltage signal is received at first terminals of the capacitors. The method further includes setting the second terminals of each channel to a second state. The method also includes applying the reference analog input voltage signal to the first terminals via a second switchable path, and thereby creating on the first terminals a non-zero settling error. The method additionally includes quantizing the settling error to obtain an estimate of the non-zero settling error. The method yet further includes comparing the estimates of the non-zero settling errors and deriving an estimation of the bandwidth mismatch.

Abstract translation: 这里的方法和装置涉及用于估计时间交织的A / D转换器中的带宽不匹配的方法。 示例性方法包括：在多个通道的每个通道中将电容器的端子预充电到第一状态，并对通过第一可切换路径施加的参考模拟输入电压信号（Vref）进行采样，由此在第一端子处接收采样的输入电压信号 电容器 该方法还包括将每个信道的第二终端设置为第二状态。 该方法还包括经由第二可切换路径将参考模拟输入电压信号施加到第一端子，从而在第一端子上产生非零稳定误差。 该方法另外包括量化沉降误差以获得非零建立误差的估计。 该方法还包括比较非零建立误差的估计并导出带宽不匹配的估计。

公开(公告)号：US09019136B2

公开(公告)日：2015-04-28

申请号：US14097451

申请日：2013-12-05

Applicant: MediaTek Inc.

Inventor： Chen-Yen Ho ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M3/32 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/452 ,  H03M2201/4233

Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.

Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。

公开(公告)号：US08896477B2

公开(公告)日：2014-11-25

申请号：US14265148

申请日：2014-04-29

Applicant: Panasonic Corporation

Inventor： Shiro Dosho ,  Masao Takayama

IPC: H03M1/50 ,  G04F10/00 ,  H03M1/18 ,  H03M1/12 ,  H03L7/087 ,  H03M1/00 ,  H03L7/081 ,  H03L7/18

CPC classification number: G04F10/005 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/18 ,  H03M2201/4233

Abstract: An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

Abstract translation: 边沿检测器包括接收环形振荡器的相位信号的触发器，在输入信号的边缘定时取消触发器的复位状态的复位器，以及对触发器的输出信号执行逻辑运算的逻辑运算器， 翻牌 相位状态检测器基于触发器的输出信号来检测在输入信号的边缘定时处发生的环形振荡器的相位状态。 时间 - 数字转换器将输入信号和逻辑运算器的输出信号之间的边沿间隔转换为数字值。 在输入信号的边缘定时处，锁存器锁存计数环形振荡器的输出信号的周期数的计数器的值。 操作者根据锁存器，相位状态检测器和时间 - 数字转换器的输出信号计算接收信号的数字值。

公开(公告)号：US08742970B2

公开(公告)日：2014-06-03

申请号：US13902638

申请日：2013-05-24

Applicant: Wolfson Microelectronics plc

Inventor： John Paul Lesso ,  John Laurence Pennock

IPC: H03M1/60 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03M1/00 ,  H03M1/1014 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/186 ,  H03M1/34 ,  H03M1/60 ,  H03M2201/4233

Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.

Abstract translation: 一种用于调节模数转换器的装置和方法。 在受控振荡器电路处接收第一和第二输入信号，该电路产生具有基于相关输入信号的脉冲速率的相应的第一和第二脉冲流。 差分电路确定第一和第二脉冲流的脉冲数的差异并输出第一数字信号。 电路还基于第一和/或第二脉冲流的脉冲数来确定与信号无关的值。 在一个实施例中，该值是第一和第二脉冲流的脉冲数的和或平均值。 该值可用于校准振荡器电路的传输特性的任何变化。 在一个实施例中，该值与参考值和传递给控制电路的调节信号进行比较以调节振荡电路的操作。

公开(公告)号：US08514121B1

公开(公告)日：2013-08-20

申请号：US13430464

申请日：2012-03-26

Applicant: Yun-Shiang Shu

Inventor： Yun-Shiang Shu

IPC: H03M1/12

CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

公开(公告)号：US4568912A

公开(公告)日：1986-02-04

申请号：US475406

申请日：1983-03-15

Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

IPC: H03M1/00 ,  H04B12/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

公开(公告)号：US4349777A

公开(公告)日：1982-09-14

申请号：US204929

申请日：1980-11-07

Applicant: Masakazu Mitamura

Inventor： Masakazu Mitamura

IPC: G01R1/28 ,  G05F1/56 ,  H03M1/00 ,  G01R27/14 ,  G05F1/58 ,  G05F1/613

CPC classification number: G05F1/561 ,  H03M1/00 ,  H03M2201/02 ,  H03M2201/14 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4266 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/814

Abstract: A plurality of metal resistance elements and a metal resistance element for compensation use are formed on a common substrate and placed under the same temperature condition. A reference current is applied to the metal resistance element for compensation use to yield an auxiliary reference voltage. A plurality of switches are individually connected in series to the reference metal resistance elements and the auxiliary reference voltage is provided to the series circuits to selectively control the switches, thereby obtaining various currents.

Abstract translation: 在公共基板上形成多个金属电阻元件和用于补偿的金属电阻元件，并置于相同的温度条件下。 将参考电流施加到用于补偿使用的金属电阻元件以产生辅助参考电压。 多个开关分别与参考金属电阻元件串联连接，并且辅助参考电压被提供给串联电路以选择性地控制开关，从而获得各种电流。