公开(公告)号：US10089263B2

公开(公告)日：2018-10-02

申请号：US15118501

申请日：2014-03-24

申请人： INTEL CORPORATION ,  Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

发明人： Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

IPC分类号： G06F13/24

摘要： A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

公开(公告)号：US20240069619A1

公开(公告)日：2024-02-29

申请号：US17898047

申请日：2022-08-29

申请人： Intel Corporation

发明人： Ko Han Wu ,  Thiam Wah Loh ,  Kenneth K. Lau ,  Wen-Kuang Yu ,  Ming-Jiun Chang ,  Andy Yeh ,  Wei Chih Chen

IPC分类号： G06F1/3234 ,  G06F1/16 ,  G06T1/00 ,  H04N5/232 ,  H04N7/18

CPC分类号： G06F1/3253 ,  G06F1/1686 ,  G06T1/0007 ,  H04N5/232411 ,  H04N7/183

摘要： A method, system, and article provide image processing with power reduction while using universal serial bus cameras.

公开(公告)号：US20230185349A1

公开(公告)日：2023-06-15

申请号：US17550197

申请日：2021-12-14

申请人： Intel Corporation

发明人： Wei Chih Chen ,  Thiam Wah Loh ,  Wei Shun Chang

IPC分类号： G06F1/28 ,  G06F1/14

CPC分类号： G06F1/28 ,  G06F1/14

摘要： An embodiment of an integrated circuit may comprise a circuit block and a power management circuit coupled to the circuit block to manage two or more power states for the circuit block and to manage a request for the circuit block to enter a requested power state of the two or more power states, set a watchdog timer in response to the request, and monitor the watchdog timer and a transition of the circuit block from a current power state to the requested power state. Other embodiments are disclosed and claimed.

公开(公告)号：US09785576B2

公开(公告)日：2017-10-10

申请号：US14227178

申请日：2014-03-27

申请人： Intel Corporation

发明人： Thiam Wah Loh ,  Per Hammarlund ,  Andreas Wasserbauer ,  Swee Chong Peter Kuan ,  Eckhard Delfs ,  Deepak A. Mathaikutty ,  Stephen J. Robinson ,  Gautham N. Chinya ,  Perry H. Wang ,  Chee Weng Tan ,  Hong Wang ,  Reza Fortas

IPC分类号： G06F12/14 ,  G11C29/52 ,  G06F21/57 ,  G11C7/10 ,  G06F21/10

CPC分类号： G06F12/1408 ,  G06F12/1491 ,  G06F21/10 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/032 ,  Y02D10/13

摘要： Systems and methods for employing hardware-assisted virtualization for implementing a secure video output path. An example processing system comprises: a memory; a shared interconnect; and a processing core communicatively coupled to the memory via the shared interconnect, the processing core to: initialize a first virtual machine and a second virtual machine; responsive to receiving a memory access transaction initiated by the first virtual machine to access a memory buffer, tag the memory access transaction with an identifier of the first virtual machine; and responsive to receiving a digital content decoder access transaction initiated by the second virtual machine, tag the digital decoder access transaction with an identifier of the second virtual machine.