公开(公告)号：US20240126599A1

公开(公告)日：2024-04-18

申请号：US18396350

申请日：2023-12-26

Applicant: Intel Corporation

Inventor： Leslie Xu ,  Toby Opferman ,  David Bradley Sheffield ,  Mukta Singh

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to manage workloads for an operating system wherein it causes programmable circuitry to cause a task of a workload to be executed with a first processor core configuration; cause the task to be executed with a second processor core configuration; compare a first performance metric of the execution of the task with the first processor core configuration to a second performance metric of the execution with the second processor core configuration; and cause to be used one of the first processor core configuration or the second processor core configuration based on the comparison.

公开(公告)号：US11461098B2

公开(公告)日：2022-10-04

申请号：US16914343

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Prashant Sethi ,  Abhimanyu K. Varde ,  Barry E. Huntley ,  Michael W. Chynoweth ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.

公开(公告)号：US20210117190A1

公开(公告)日：2021-04-22

申请号：US17134249

申请日：2020-12-25

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Russell C. Arnold ,  Vedvyas Shanbhogue

IPC: G06F9/30 ,  G06F9/455

Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.

公开(公告)号：US09239801B2

公开(公告)日：2016-01-19

申请号：US13910333

申请日：2013-06-05

Applicant: Intel Corporation

Inventor： Baiju V. Patel ,  Xiaoning Li ,  H P. Anvin ,  Asit K. Mallick ,  Gilbert Neiger ,  James B. Crossland ,  Toby Opferman ,  Atul A. Khare ,  Jason W. Brandt ,  James S. Coke ,  Brian L. Vajda

IPC: G06F12/14 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F12/145 ,  G06F8/434 ,  G06F9/30105 ,  G06F9/30134 ,  G06F21/52

Abstract: An example processing system may comprise: a lower stack bound register configured to store a first memory address, the first memory address identifying a lower bound of a memory addressable via a stack segment; an upper stack bound register configured to store a second memory address, the second memory address identifying an upper bound of the memory addressable via the stack segment; and a stack bounds checking logic configured to detect unauthorized stack pivoting, by comparing a memory address being accessed via the stack segment with at least one of the first memory address and the second memory address.

Abstract translation: 示例处理系统可以包括：下堆叠绑定寄存器，被配置为存储第一存储器地址，第一存储器地址标识经由堆栈段可寻址的存储器的下限; 上堆叠绑定寄存器，其被配置为存储第二存储器地址，所述第二存储器地址通过所述堆栈段识别所述存储器可寻址的上限; 并且通过将经由所述堆栈段访问的存储器地址与所述第一存储器地址和所述第二存储器地址中的至少一个进行比较来配置用于检测未授权堆栈枢转的堆栈边界检查逻辑。

公开(公告)号：US11957974B2

公开(公告)日：2024-04-16

申请号：US17168299

申请日：2021-02-05

Applicant: Intel Corporation

Inventor： Makarand Dharmapurikar ,  Rajabali Koduri ,  Vijay Bahirji ,  Toby Opferman ,  Scott G. Christian ,  Rajeev Penmatsa ,  Selvakumar Panneer

IPC: A63F13/355

CPC classification number: A63F13/355

Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.

公开(公告)号：US20220374278A1

公开(公告)日：2022-11-24

申请号：US17882175

申请日：2022-08-05

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/50 ,  G06F9/38 ,  G06F9/48 ,  G06F9/30 ,  G06F9/448

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US20220262427A1

公开(公告)日：2022-08-18

申请号：US17178015

申请日：2021-02-17

Applicant: Intel Corporation

Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/402

Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

公开(公告)号：US20210096908A1

公开(公告)日：2021-04-01

申请号：US16586706

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Toby Opferman ,  Eliezer Weissmann ,  Robert Valentine ,  Russell Cameron Arnold

IPC: G06F9/48 ,  G06F9/38

Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.

公开(公告)号：US12165686B2

公开(公告)日：2024-12-10

申请号：US17178015

申请日：2021-02-17

Applicant: Intel Corporation

Inventor： Nivedha Krishnakumar ,  Virendra Vikramsinh Adsure ,  Jaya Jeyaseelan ,  Nadav Bonen ,  Barnes Cooper ,  Toby Opferman ,  Vijay Bahirji ,  Chia-Hung Kuo

IPC: G11C11/406 ,  G11C5/14 ,  G11C11/402 ,  G11C11/4074

Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.

公开(公告)号：US10346167B2

公开(公告)日：2019-07-09

申请号：US15384300

申请日：2016-12-19

Applicant: INTEL CORPORATION

Inventor： Toby Opferman ,  James B. Crossland ,  Jason W. Brandt ,  Beeman C. Strong

IPC: G06F11/00 ,  G06F9/30 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F11/30

Abstract: Methods and apparatuses for generating a suppressed address trace are described. In some embodiments, a processor includes a trace generator having a trace suppressor that outputs a suppressed address trace for instructions executed by the processor. In some embodiments, a method to generate a suppressed address trace for a processor includes generating a suppressed address trace of executed instructions from a trace suppressor of a trace generator of the processor.