公开(公告)号：US20160372377A1

公开(公告)日：2016-12-22

申请号：US15221515

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US20240347394A1

公开(公告)日：2024-10-17

申请号：US18757060

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/66477 ,  H10B10/12

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20200235014A1

公开(公告)日：2020-07-23

申请号：US16844588

申请日：2020-04-09

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20190035690A1

公开(公告)日：2019-01-31

申请号：US16020722

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/11 ,  H01L27/092 ,  H01L21/28 ,  H01L27/088 ,  H01L21/8234

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.