中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.015 seconds)

    PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN
    1.
    发明申请
    PULSED LASER ANNEAL PROCESS FOR TRANSISTORS WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN 有权
    具有部分熔体的激光源激光器的脉冲激光退火过程

    公开(公告)号：US20150200301A1

    公开(公告)日：2015-07-16

    申请号：US14667544

    申请日：2015-03-24

    Applicant: Intel Corporation

    Inventor： Jacob Jensen ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

    IPC: H01L29/78 ,  H01L29/165 ,  H01L29/417 ,  H01L29/08 ,  H01L29/10

    CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

    Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

    Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

    DIFFUSED TIP EXTENSION TRANSISTOR
    2.
    发明申请
    DIFFUSED TIP EXTENSION TRANSISTOR 有权

    公开(公告)号：US20210050448A1

    公开(公告)日：2021-02-18

    申请号：US17085981

    申请日：2020-10-30

    Applicant: Intel Corporation

    Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

    IPC: H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267

    Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

    PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN
    7.
    发明申请
    PULSED LASER ANNEAL PROCESS FOR TRANSISTOR WITH PARTIAL MELT OF A RAISED SOURCE-DRAIN 审中-公开
    用于具有部分熔体的晶体管的脉冲激光退火过程

    公开(公告)号：US20160372599A1

    公开(公告)日：2016-12-22

    申请号：US15246468

    申请日：2016-08-24

    Applicant: Intel Corporation

    Inventor： Jacob JENSEN ,  Tahir GHANI ,  Mark Y. LIU ,  Harold KENNEL ,  Robert JAMES

    IPC: H01L29/78 ,  H01L29/417 ,  H01L21/268 ,  H01L21/324 ,  H01L21/265 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    Abstract: A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack disposed there between. The raised semiconductor source/drains comprise a super-activated dopant region above a melt depth and an activated dopant region below the melt depth. The super-activated dopant region has a higher activated dopant concentration than the activated dopant region and/or has an activated dopant concentration that is constant throughout the melt region. A fin is formed on a substrate and a semiconductor material or a semiconductor material stack is deposited on regions of the fin disposed on opposite sides of a channel region to form raised source/drains. A pulsed laser anneal is performed to melt only a portion of the deposited semiconductor material above a melt depth.

    Abstract translation: 一种非平面晶体管，其包括设置在半导体鳍片的相对端上的部分熔融的凸起半导体源极/漏极，其间设置有栅极堆叠。 升高的半导体源极/漏极包括在熔体深度之上的超激活掺杂剂区域和低于熔体深度的活化掺杂剂区域。 超活化掺杂剂区域具有比活化的掺杂剂区域更高的活化掺杂剂浓度和/或具有在整个熔融区域中恒定的活化的掺杂剂浓度。 翅片形成在基板上，并且半导体材料或半导体材料堆叠沉积在设置在沟道区域的相对侧上的翅片的区域上以形成升高的源极/漏极。 进行脉冲激光退火以仅将融化的半导体材料的一部分熔化在熔体深度之上。

    DIFFUSED TIP EXTENSION TRANSISTOR
    9.
    发明申请
    DIFFUSED TIP EXTENSION TRANSISTOR 审中-公开
    扩展尖端延伸晶体管

    公开(公告)号：US20160380102A1

    公开(公告)日：2016-12-29

    申请号：US15038969

    申请日：2013-12-27

    Applicant: Pratik PATEL ,  Jami A. WIEDEMER ,  Paul A. PACKAN ,  INTEL CORPORATION

    Inventor： Pratik A. PATEL ,  Mark Y. LIU ,  Jami A. WIEDEMER ,  Paul A. PACKAN

    IPC: H01L29/78 ,  H01L29/24 ,  H01L21/225 ,  H01L29/66 ,  H01L21/324 ,  H01L29/08 ,  H01L29/267

    CPC classification number: H01L29/7848 ,  H01L21/2253 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66492 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7851

    Abstract: A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

    Abstract translation: 一种方法，包括在鳍片的接合区域中形成开口并在基底上延伸的方法; 在开口中引入掺杂的半导体材料; 并对掺杂的半导体材料进行热处理。 一种方法，包括在从衬底延伸的翅片上形成栅电极; 在所述鳍片的邻近所述栅电极的相对侧上形成开口; 在开口中引入掺杂的半导体材料; 并且热处理足以引起掺杂半导体材料中的掺杂剂扩散的掺杂​​半导体材料。 一种装置，包括横跨从基板延伸的翅片的栅电极; 以及半导体材料填充的开口，在栅电极的相邻相邻两侧的接合区域中，其中半导体材料包括掺杂剂。

    INTEGRATED CIRCUITS WITH SELETIVE GATE ELECTRODE RECESS
    10.
    发明申请
    INTEGRATED CIRCUITS WITH SELETIVE GATE ELECTRODE RECESS 审中-公开
    集成电路与电极电极接触

    公开(公告)号：US20160372377A1

    公开(公告)日：2016-12-22

    申请号：US15221515

    申请日：2016-07-27

    Applicant: Intel Corporation

    Inventor： Srijit Mukherjee ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

    Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

    Abstract translation: 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

Patent Agency Ranking