公开(公告)号：US20150079776A1

公开(公告)日：2015-03-19

申请号：US14548215

申请日：2014-11-19

申请人： Intel Corporation

发明人： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC分类号： H01L21/8234 ,  H01L21/28

CPC分类号： H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

摘要： Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

摘要翻译： 集成电路包括具有选择性凹陷栅电极的MOSFET。 具有具有减小的电容耦合面积到相邻源极和漏极接触金属化的凹陷栅电极的晶体管与具有非凹陷且具有较大z高度的栅电极的晶体管一起提供。 在实施例中，模拟电路采用具有给定z高度的栅电极的晶体管，而逻辑门采用具有较小z高度的凹陷栅电极的晶体管。 在实施例中，基本上平面的栅电极的子集被选择性地回蚀以基于在电路内的给定晶体管的应用来区分栅电极的高度。

公开(公告)号：US20210043520A1

公开(公告)日：2021-02-11

申请号：US17068121

申请日：2020-10-12

申请人： Intel Corporation

发明人： Jeffrey S. LEIB ,  Srijit MUKHERJEE ,  Vinay BHAGWAT ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L21/8238 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

公开(公告)号：US20240178071A1

公开(公告)日：2024-05-30

申请号：US18435609

申请日：2024-02-07

申请人： Intel Corporation

发明人： Jeffrey S. LEIB ,  Srijit MUKHERJEE ,  Vinay BHAGWAT ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L21/8238 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/823814 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76816 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0924 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7854 ,  H10B10/12

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

公开(公告)号：US20220102506A1

公开(公告)日：2022-03-31

申请号：US17033373

申请日：2020-09-25

申请人： Intel Corporation

发明人： Kevin COOK ,  Anand S. MURTHY ,  Gilbert DEWEY ,  Nazila HARATIPOUR ,  Chi-Hing CHOI ,  Jitendra Kumar JHA ,  Srijit MUKHERJEE

IPC分类号： H01L29/40 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/45 ,  H01L29/417

摘要： Embodiments disclosed herein include complementary metal-oxide-semiconductor (CMOS) devices and methods of making such devices. In an embodiment, a CMOS device comprises a first transistor with a first conductivity type, where the first transistor comprises a first source region and a first drain region, and a first interface material over the first source region and the first drain region. In an embodiment, the CMOS device further comprises a second transistor with a second conductivity type that is opposite form the first conductivity type, where the second transistor comprises a second source region and a second drain region, and a second interface material over the second source region and the second drain region.

公开(公告)号：US20240347394A1

公开(公告)日：2024-10-17

申请号：US18757060

申请日：2024-06-27

申请人： Intel Corporation

发明人： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H10B10/00

CPC分类号： H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/495 ,  H01L29/66477 ,  H10B10/12

摘要： Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20240332392A1

公开(公告)日：2024-10-03

申请号：US18737616

申请日：2024-06-07

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L21/28 ,  H01L21/285 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/45 ,  H01L21/28088 ,  H01L21/28518 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/7851

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20230042218A1

公开(公告)日：2023-02-09

申请号：US17967511

申请日：2022-10-17

申请人： Intel Corporation

发明人： Jeffrey S. LEIB ,  Srijit MUKHERJEE ,  Vinay BHAGWAT ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L23/522 ,  H01L29/51 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L21/28 ,  H01L29/78 ,  H01L21/311 ,  H01L27/11 ,  H01L29/417 ,  H01L23/532 ,  H01L21/033 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L21/285

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.

公开(公告)号：US20210408258A1

公开(公告)日：2021-12-30

申请号：US16912118

申请日：2020-06-25

申请人： Intel Corporation

发明人： Dan S. LAVRIC ,  Glenn A. GLASS ,  Thomas T. TROEGER ,  Suresh VISHWANATH ,  Jitendra Kumar JHA ,  John F. RICHARDS ,  Anand S. MURTHY ,  Srijit MUKHERJEE

IPC分类号： H01L29/45 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/49 ,  H01L21/28 ,  H01L21/285 ,  H01L29/66

摘要： Approaches for fabricating an integrated circuit structure including a titanium silicide material, and the resulting structures, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate, a gate electrode over the top and adjacent to the sidewalls of a portion of the semiconductor fin. A titanium silicide material is in direct contact with each of first and second epitaxial semiconductor source or drain structures at first and second sides of the gate electrode. The titanium silicide material is conformal with and hermetically sealing a non-flat topography of each of the first and second epitaxial semiconductor source or drain structures. The titanium silicide material has a total atomic composition including 95% or greater stoichiometric TiSi2.

公开(公告)号：US20200235014A1

公开(公告)日：2020-07-23

申请号：US16844588

申请日：2020-04-09

申请人： Intel Corporation

发明人： Srijit MUKHERJEE ,  Christopher J. WIEGAND ,  Tyler J. WEEKS ,  Mark Y. LIU ,  Michael L. HATTENDORF

IPC分类号： H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49

摘要： Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US20200013680A1

公开(公告)日：2020-01-09

申请号：US16516693

申请日：2019-07-19

申请人： Intel Corporation

发明人： Jeffrey S. LEIB ,  Srijit MUKHERJEE ,  Vinay BHAGWAT ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC分类号： H01L21/8238 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/08 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/092 ,  H01L29/51 ,  H01L21/285 ,  H01L21/28 ,  H01L21/033 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a P-type semiconductor device above a substrate and including first and second semiconductor source or drain regions adjacent first and second sides of a first gate electrode. A first metal silicide layer is directly on the first and second semiconductor source or drain regions. An N-type semiconductor device includes third and fourth semiconductor source or drain regions adjacent first and second sides of a second gate electrode. A second metal silicide layer is directly on the third and fourth semiconductor source or drain regions, respectively. The first metal silicide layer comprises at least one metal species not included in the second metal silicide layer.