公开(公告)号：US10651093B2

公开(公告)日：2020-05-12

申请号：US16020722

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L29/49 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/28

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US11183432B2

公开(公告)日：2021-11-23

申请号：US16844588

申请日：2020-04-09

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/49

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US12165928B2

公开(公告)日：2024-12-10

申请号：US17505468

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L Hattendorf

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H10B10/00

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

公开(公告)号：US10020232B2

公开(公告)日：2018-07-10

申请号：US15221515

申请日：2016-07-27

Applicant: Intel Corporation

Inventor： Srijit Mukherjee ,  Christopher J. Wiegand ,  Tyler J. Weeks ,  Mark Y. Liu ,  Michael L. Hattendorf

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/11 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823821 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/495 ,  H01L29/66477

Abstract: Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. In embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. In embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.