公开(公告)号：US20150277910A1

公开(公告)日：2015-10-01

申请号：US14228016

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： EDWARD T. GROCHOWSKI ,  VICTOR W. LEE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F9/3005 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/30134

Abstract: An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

Abstract translation: 描述了使用谓词寄存器执行指令的装置和方法。 例如，处理器的一个实施例包括：寄存器集合，其包括用于存储一组谓词条件位的谓词寄存器，所述谓词条件位指定要保留或丢弃特定预测指令序列的结果; 并且通过将状态值从寄存器集中的处理器控制寄存器复制到谓词寄存器来执行第一谓词指令以指示新的预测指令序列的开始的谓词执行逻辑。 在另一个实施例中，谓词寄存器中的谓词条件位将响应于第一谓词指令移位，以便在与谓词指令序列相关联的新条件值的谓词寄存器内释放空间。

公开(公告)号：US20150186077A1

公开(公告)日：2015-07-02

申请号：US14142734

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： VICTOR W. LEE

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/0688 ,  G06F3/0604 ,  G06F3/0638 ,  G06F9/3004 ,  G06F9/30167 ,  G06F9/38 ,  G06F9/3832 ,  G06F13/28 ,  G06F2003/0695

Abstract: A processor of an aspect includes an on-die programmable architecturally-visible storage. The processor also includes a decode unit to receive a data access instruction of an instruction set of the processor. The data access instruction to indicate a data address that is to be associated with data to be stored in the on-die programmable architecturally-visible storage, to indicate a data size associated with the data to be stored in the on-die programmable architecturally-visible storage, and to indicate a destination storage location of the processor. An execution unit is coupled with the decode unit and the on-die programmable architecturally-visible storage. The execution unit is on-die with the on-die programmable storage. The execution unit is operable, in response to the data access instruction, to store the data, which is associated with the data address and the data size, in the destination storage location that is to be indicated by the instruction.

Abstract translation: 一个方面的处理器包括可在模块上可编程的架构可见存储器。 处理器还包括用于接收处理器的指令集的数据访问指令的解码单元。 数据访问指令，用于指示要与要存储在片上可编程结构可见存储器中的数据相关联的数据地址，以指示与待存储在片上可编程结构可见存储器中的数据相关联的数据大小， 可见存储，并指示处理器的目的地存储位置。 执行单元与解码单元和片上可编程结构可见存储器耦合。 执行单元与片上可编程存储器在一起。 执行单元响应于数据访问指令可操作地将与数据地址和数据大小相关联的数据存储在由指令指示的目的地存储单元中。

公开(公告)号：US20160239431A1

公开(公告)日：2016-08-18

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： SHENG LI ,  SANJAY KUMAR ,  VICTOR W. LEE ,  RAJESH M. SANKARAN ,  SUBRAMANYA R. DULLOOR

IPC: G06F12/10 ,  G06F12/08

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

Abstract translation: 处理器包括处理核心，用于执行包括经由非永久性高速缓冲存储器与永久存储器编码事务的指令的应用程序，其中事务是创建从虚拟地址空间到由存储器区域标识符（ MRID），并且使用其中高速缓存行与高速缓存行状态相关联的MRID和高速缓存控制器将非持续高速缓存的高速缓存行标记为响应于检测到故障事件而选择性地 基于高速缓存行状态将高速缓存行的内容推送到由MRID标识的存储器区域。