公开(公告)号：US20170039139A1

公开(公告)日：2017-02-09

申请号：US15297084

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： ANDREY KLUCHNIKOV ,  JAYESH IYER ,  SERGEY Y. SHISHLOV ,  BORIS A. BABAYAN

IPC: G06F12/0844 ,  G06F3/06 ,  G06F12/0842 ,  G06F12/0811 ,  G06F12/084

CPC classification number: G06F12/0844 ,  G06F3/0613 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F13/18 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/452

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract translation: 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。

公开(公告)号：US20150277910A1

公开(公告)日：2015-10-01

申请号：US14228016

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： EDWARD T. GROCHOWSKI ,  VICTOR W. LEE ,  SERGEY A. ROZHKOV ,  BORIS A. BABAYAN

IPC: G06F9/30

CPC classification number: G06F9/30076 ,  G06F9/3005 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/30134

Abstract: An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.

Abstract translation: 描述了使用谓词寄存器执行指令的装置和方法。 例如，处理器的一个实施例包括：寄存器集合，其包括用于存储一组谓词条件位的谓词寄存器，所述谓词条件位指定要保留或丢弃特定预测指令序列的结果; 并且通过将状态值从寄存器集中的处理器控制寄存器复制到谓词寄存器来执行第一谓词指令以指示新的预测指令序列的开始的谓词执行逻辑。 在另一个实施例中，谓词寄存器中的谓词条件位将响应于第一谓词指令移位，以便在与谓词指令序列相关联的新条件值的谓词寄存器内释放空间。