公开(公告)号：US20240193109A1

公开(公告)日：2024-06-13

申请号：US18444379

申请日：2024-02-16

Applicant: Intel Corporation

Inventor： Michelle M. WIGTON ,  Kambiz R. MUNSHI ,  Zhongyao Linda GU ,  Mohammad M. RASHID ,  Victor LAU ,  Jing LING

IPC: G06F13/16 ,  H10B12/00

CPC classification number: G06F13/1689 ,  H10B12/00

Abstract: Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.