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    DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY
    3.
    发明申请
    DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY 有权

    公开(公告)号：US20220091764A1

    公开(公告)日：2022-03-24

    申请号：US17540847

    申请日：2021-12-02

    Applicant: Intel Corporation

    Inventor： Sreenivas MANDAVA ,  Jing LING

    IPC: G06F3/06

    Abstract: A memory controller including memory address decode circuitry that detects silent data errors that occur in the memory address decode circuitry during runtime is provided. The memory address decode circuitry includes address decode circuitry to covert a received physical address to a memory address, reverse address decode circuitry to convert the memory address to a second physical address and address compare circuitry to compare the received physical address and the second physical address to detect a silent error.

    APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER
    5.
    发明公开
    APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY PHY IN A MEMORY CONTROLLER 审中-公开

    公开(公告)号：US20240193109A1

    公开(公告)日：2024-06-13

    申请号：US18444379

    申请日：2024-02-16

    Applicant: Intel Corporation

    Inventor： Michelle M. WIGTON ,  Kambiz R. MUNSHI ,  Zhongyao Linda GU ,  Mohammad M. RASHID ,  Victor LAU ,  Jing LING

    IPC: G06F13/16 ,  H10B12/00

    CPC classification number: G06F13/1689 ,  H10B12/00

    Abstract: Memory power consumption is reduced without increasing latency of memory read access. When inactive, power consumption is reduced in a PHY in a memory controller by disabling receiver bias circuitry and a clock network in the PHY. The memory controller sends two command-based signals to the PHY to enable the PHY to enable the receiver bias circuitry and the clock network in the PHY to transition the memory from a low power state to an active power state prior to or at the time of receiving command from the memory controller. A first command-based signal is an early command indication signal that is sent before any command. The second command-based signal is a read indication signal that is sent synchronous with every read command. Upon receiving these signals, the PHY enables the clock network and receiver bias circuitry.

    FAST MEMORY ECC ERROR CORRECTION
    6.
    发明申请
    FAST MEMORY ECC ERROR CORRECTION 有权

    公开(公告)号：US20220107866A1

    公开(公告)日：2022-04-07

    申请号：US17550859

    申请日：2021-12-14

    Applicant: Intel Corporation

    Inventor： Jing LING ,  Wei P. CHEN ,  Rajat AGARWAL

    IPC: G06F11/10 ,  G06F11/14

    Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow. The read data is stored in a read data buffer at the memory controller when the read data is received from memory. Once the ECC circuitry detects an error in the read data, the retry flow enables access to that data from the read data buffer instead of reading the data from memory for the second time. Access to the data from the read data buffer reduces the overall time needed for the correction flow compared to a retry flow that rereads the data from memory.

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