公开(公告)号：US20180122779A1

公开(公告)日：2018-05-03

申请号：US15699750

申请日：2017-09-08

Applicant: Intel Corporation

Inventor： Pete D. VOGT ,  Andre SCHAEFER ,  Warren MORROW ,  John B. HALBERT ,  Jin KIM ,  Kenneth D. SHOEMAKER

IPC: H01L25/065 ,  H01L27/108 ,  H01L23/48 ,  G11C5/06 ,  H01L23/00

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

公开(公告)号：US20190304953A1

公开(公告)日：2019-10-03

申请号：US16424355

申请日：2019-05-28

Applicant: Intel Corporation

Inventor： Pete D. VOGT ,  Andre SCHAEFER ,  Warren MORROW ,  John B. HALBERT ,  Jin KIM ,  Kenneth D. SHOEMAKER

IPC: H01L25/065 ,  H01L23/48 ,  G11C5/06 ,  H01L27/108

Abstract: A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.