中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.012 seconds)

    Distributed and scalable all-digital low dropout integrated voltage regulator
    3.
    发明授权
    Distributed and scalable all-digital low dropout integrated voltage regulator 有权

    公开(公告)号：US11774919B2

    公开(公告)日：2023-10-03

    申请号：US17125768

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

    IPC: G05B11/42 ,  G05B11/12 ,  G05F1/46

    CPC classification number: G05B11/12 ,  G05F1/46

    Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY
    4.
    发明申请
    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY 有权

    公开(公告)号：US20210242872A1

    公开(公告)日：2021-08-05

    申请号：US17020667

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

    IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

    Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

    All-digital voltage monitor (ADVM) with single-cycle latency
    5.
    发明授权
    All-digital voltage monitor (ADVM) with single-cycle latency 有权

    公开(公告)号：US11211935B2

    公开(公告)日：2021-12-28

    申请号：US17020667

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

    IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

    Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

    DISTRIBUTED AND SCALABLE ALL-DIGITAL LOW DROPOUT INTEGRATED VOLTAGE REGULATOR
    6.
    发明申请
    DISTRIBUTED AND SCALABLE ALL-DIGITAL LOW DROPOUT INTEGRATED VOLTAGE REGULATOR 有权

    公开(公告)号：US20210240142A1

    公开(公告)日：2021-08-05

    申请号：US17125768

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

    IPC: G05B11/42 ,  G05F1/46

    Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

Patent Agency Ranking