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    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT
    1.
    发明申请
    TECHNIQUES FOR MULTI-READ AND MULTI-WRITE OF MEMORY CIRCUIT 有权

    公开(公告)号：US20210043251A1

    公开(公告)日：2021-02-11

    申请号：US17001432

    申请日：2020-08-24

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    Techniques for multi-read and multi-write of memory circuit
    2.
    发明授权
    Techniques for multi-read and multi-write of memory circuit 有权

    公开(公告)号：US10755771B2

    公开(公告)日：2020-08-25

    申请号：US16226385

    申请日：2018-12-19

    Applicant: Intel Corporation

    Inventor： Muhammad M. Khellah ,  Somnath Paul ,  Charles Augustine ,  Turbo Majumder ,  Suyoung Bang

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12 ,  G11C7/10 ,  G11C11/418 ,  G11C7/22

    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.

    Distributed and scalable all-digital low dropout integrated voltage regulator
    4.
    发明授权
    Distributed and scalable all-digital low dropout integrated voltage regulator 有权

    公开(公告)号：US11774919B2

    公开(公告)日：2023-10-03

    申请号：US17125768

    申请日：2020-12-17

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Wootaek Lim ,  Eric Samson ,  Charles Augustine ,  Muhammad Khellah

    IPC: G05B11/42 ,  G05B11/12 ,  G05F1/46

    CPC classification number: G05B11/12 ,  G05F1/46

    Abstract: A distributed and scalable all-digital LDO (D-DLDO) voltage regulator allowing rapid scaling across technology nodes. The distributed DLDO includes many tillable DLDO units regulating a single supply voltage with a shared power distribution network (PDN). The D-DLDO includes an all-digital proportional-integral-derivative (PID) controller that receives a first code indicative of a voltage behavior on a power supply rail. A droop detector is provided to compare the first code with a threshold to determine a droop event, wherein information about the droop event is provided to the PID controller, wherein the PID controller generates a second code according to the first code and the information about the droop event. The DLDO includes a plurality of power gates that receive the second code.

    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY
    5.
    发明申请
    ALL-DIGITAL VOLTAGE MONITOR (ADVM) WITH SINGLE-CYCLE LATENCY 有权

    公开(公告)号：US20210242872A1

    公开(公告)日：2021-08-05

    申请号：US17020667

    申请日：2020-09-14

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Eric Samson ,  Wootaek Lim ,  Charles Augustine ,  Muhammad Khellah

    IPC: H03L7/081 ,  G04F10/00 ,  H03L7/085

    Abstract: An all-digital voltage monitor (ADVM) generates a multi-bit output code that changes in proportion to a voltage being monitored, by leveraging the voltage impact on a gate delay. ADVM utilizes a simple delay chain, which receives a clock-cycle-long pulse every clock cycle, such that the monitored supply voltage is sampled for one full cycle every cycle. The outputs of all delay cells of the delay chain collectively represents a current voltage state as a digital thermometer code. In AVDM, a voltage droop event thus results in a decrease in the output code from a nominal value, while an overshoot results in an increase in the output code.

    Calibrated biasing of sleep transistor in integrated circuits
    8.
    发明授权
    Calibrated biasing of sleep transistor in integrated circuits 有权

    公开(公告)号：US10454476B2

    公开(公告)日：2019-10-22

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS
    9.
    发明申请
    CALIBRATED BIASING OF SLEEP TRANSISTOR IN INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20190044512A1

    公开(公告)日：2019-02-07

    申请号：US16145598

    申请日：2018-09-28

    Applicant: Intel Corporation

    Inventor： Suyoung Bang ,  Muhammad Khellah ,  Charles Augustine ,  Pascal Meinerzhagen ,  Minki Cho

    IPC: H03K19/00

    CPC classification number: H03K19/0016 ,  H03K19/0013

    Abstract: Embodiments include apparatuses, methods, and systems associated with biasing a sleep transistor (also referred to as a power gate transistor) in an integrated circuit. The sleep transistor may be coupled between a load circuit and a power rail, the sleep transistor to be on in an active mode to provide the supply voltage to the load circuit, and to be off in a sleep mode to disconnect the load circuit from the power rail. The bias circuit may be coupled to the gate terminal of the sleep transistor to provide a calibrated gate voltage to the gate terminal during the sleep mode. The calibrated gate voltage may be based on a subthreshold leakage current and a gate-induced drain leakage (GIDL) current of the sleep transistor or a replica sleep transistor designed to replicate the leakage current of the sleep transistor. Other embodiments may be described and claimed.

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