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公开(公告)号:US20220350499A1
公开(公告)日:2022-11-03
申请号:US17745453
申请日:2022-05-16
Applicant: Intel Corporation
Inventor: Shaopeng HE , Yadong LI , Anjali Singhai JAIN , Kenneth G. KEELS , Andrzej SAWULA , Kun TIAN , Ashok RAJ , Rupin H. VAKHARWALA , Rajesh M. SANKARAN , Saurabh GAYEN , Baolu LU , Yan ZHAO
Abstract: As described herein, for a selected process identifier and virtual address, a page fault arising from multiple sources can be solved by a one-time operation. The selected process identifier can include a virtual function (VF) identifier or process address space identifier (PASID). In some examples, solving a page fault arising from multiple sources by a one-time operation comprises invoking a page fault handler to determine an address translation.
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公开(公告)号:US20220261178A1
公开(公告)日:2022-08-18
申请号:US17688710
申请日:2022-03-07
Applicant: Intel Corporation
Inventor: Shaopeng HE , Yadong LI , Anjali Singhai JAIN , Kun TIAN , Yan ZHAO , Yaozu DONG , Baolu LU , Rajesh M. SANKARAN , Eliel LOUZOUN , Rupin H. VAKHARWALA , David HARRIMAN , Saurabh GAYEN , Philip LANTZ , Israel BEN SHAHAR , Kenneth G. KEELS
Abstract: Examples described herein relate to a packet processing device that includes circuitry to receive an address translation for a virtual to physical address prior to receipt of a GPUDirect remote direct memory access (RDMA) operation, wherein the address translation is provided at initiation of a process executed by a host system and circuitry to apply the address translation for a received GPUDirect RDMA operation.
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公开(公告)号:US20220188965A1
公开(公告)日:2022-06-16
申请号:US17598267
申请日:2019-06-24
Applicant: Intel Corporation
Abstract: An apparatus and method for scheduling workloads across virtualized graphics processors. For example, one embodiment of a graphics processing apparatus comprises first graphics processing resources to process graphics commands and execute graphics data; workload scheduling circuitry to schedule workloads for execution on the first graphics processing resources; and workload queuing circuitry to implement a local queue to store local workload entries, each local workload entry associated with a locally-submitted workload and an external workload queue to store external workload entries, each external workload entry associated with an externally-submitted workload submitted for execution by an external graphics processing apparatus, in one embodiment, the workload scheduling circuitry schedules the locally-submitted workloads identified in the local queue and externally-submitted workloads identified in the external workload queue for processing by specified portions of the first graphics processing resources.
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公开(公告)号:US20220197805A1
公开(公告)日:2022-06-23
申请号:US17479954
申请日:2021-09-20
Applicant: Intel Corporation
Inventor: Shaopeng HE , Anjali Singhai JAIN , Patrick MALONEY , Yadong LI , Chih-Jen CHANG , Kun TIAN , Yan ZHAO , Rajesh M. SANKARAN , Ashok RAJ
IPC: G06F12/0831 , G06F12/1009 , G06F9/455
Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.
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