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公开(公告)号：US20250123988A1
公开(公告)日：2025-04-17
申请号：US19000121
申请日：2024-12-23
Applicant: Intel Corporation
Inventor： Liron ELMALEH , Eliel LOUZOUN , Yosef Hai AMAR , Alon MEIR
Abstract: Examples described herein relate to a network interface device. The network interface device includes a host interface; a network interface; and a direct memory access (DMA) circuitry. In some examples, the host interface includes circuitry to: apply a first configuration of Peripheral Component Interconnect Express (PCIe) upstream ports and downstream ports and without reboot of the network interface device, apply a second configuration to adjust routing of communication among devices coupled to the PCIe upstream ports and downstream ports.
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公开(公告)号：US20200228467A1
公开(公告)日：2020-07-16
申请号：US16833401
申请日：2020-03-27
Applicant: Intel Corporation
Inventor： Eliel LOUZOUN , Anjali Singhai JAIN , Ben-Zion FRIEDMAN
IPC: H04L12/861 , H04L12/935
Abstract: Examples described herein relate to an apparatus including at least one memory and at least one processor communicatively coupled to the at least one memory, the at least one processor to: allocate a scheduler to an egress port and based on unavailability of an egress port, allocate the scheduler to a second egress port to cause any packet allocated to a transmit queue associated with the scheduler to be transmitted using the second egress port. In some examples, a system receives a packet at a port on a network interface, associates a port group with the packet, determines a receive queue for the packet, and copies the packet to the determined receive queue. The port group can be adjusted to remove the port or to add a second port.
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公开(公告)号：US20240388529A1
公开(公告)日：2024-11-21
申请号：US18665632
申请日：2024-05-16
Applicant: Intel Corporation
Inventor： Eliel LOUZOUN , Manasi DEVAL , Stephen DOYLE , Noam ELATI , Patrick FLEMING , Gregory BOWERS
Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.
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公开(公告)号：US20220197859A1
公开(公告)日：2022-06-23
申请号：US17690950
申请日：2022-03-09
Applicant: Intel Corporation
Inventor： Janusz JURSKI , Myron LOEWEN , Mariusz ORIOL , Patrick SCHOELLER , Jerry BACKER , Richard Marian THOMAIYAR , Eliel LOUZOUN , Piotr MATUSZCZAK
Abstract: Methods and apparatus for scalable MCTP infrastructure. A system is split into independent MCTP domains, wherein each MCTP domain uses Endpoint Identifiers (EIDs) for endpoint devices within the MCTP domain in a manner similar to conventional MCTP operations. A new class of MCTP devices (referred to as a Domain Controllers) is provided to enable inter-domain communication and communication with global devices. Global traffic originators or receivers like a BMC (Baseboard Management Controller), Infrastructure Processing Unit (IPU), Smart NIC (Network Interface Card), Debugger, or PROT (Platform Root or Trust) discover and establish two-way communication through the Domain Controllers to any of the devices in the target domain(s). The Domain Controllers are configured to implement tunneled connections between global devices and domain endpoint devices. The tunneled connections may employ encapsulated messages with outer and inner headers and/or augmented MCTP messages with repurposed fields used to store source and destination EIDs.
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Patent Agency Ranking
公开(公告)号：US20220261178A1
公开(公告)日：2022-08-18
申请号：US17688710
申请日：2022-03-07
Applicant: Intel Corporation
Inventor： Shaopeng HE , Yadong LI , Anjali Singhai JAIN , Kun TIAN , Yan ZHAO , Yaozu DONG , Baolu LU , Rajesh M. SANKARAN , Eliel LOUZOUN , Rupin H. VAKHARWALA , David HARRIMAN , Saurabh GAYEN , Philip LANTZ , Israel BEN SHAHAR , Kenneth G. KEELS
Abstract: Examples described herein relate to a packet processing device that includes circuitry to receive an address translation for a virtual to physical address prior to receipt of a GPUDirect remote direct memory access (RDMA) operation, wherein the address translation is provided at initiation of a process executed by a host system and circuitry to apply the address translation for a received GPUDirect RDMA operation.
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公开(公告)号：US20220141133A1
公开(公告)日：2022-05-05
申请号：US17648196
申请日：2022-01-18
Applicant: Intel Corporation
Inventor： Eliel LOUZOUN , Manasi DEVAL , Stephen DOYLE , Noam ELATI , Patrick FLEMING , Gregory BOWERS
Abstract: An apparatus, a method, and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.
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公开(公告)号：US20220086226A1
公开(公告)日：2022-03-17
申请号：US17483458
申请日：2021-09-23
Applicant: Intel Corporation
Inventor： Anjali Singhai JAIN , Noam ELATI , Eliel LOUZOUN , Daniel DALY
IPC: H04L67/1097 , G06F9/455 , G06F13/28
Abstract: Examples described herein relate to a network interface device comprising: a device interface; at least one processor; a direct memory access (DMA) device; and a packet processing circuitry. In some examples, the at least one processor, when operational, is configured to: in connection with a first operation: perform a format translation of a first descriptor from a first format associated with an emulated device to a second format associated with the packet processing circuitry and provide, to the packet processing circuitry, the translated first descriptor. In some examples, the at least one processor, when operational, is configured to: in connection with a second operation: perform a descriptor format translation of a second descriptor from the second format associated with the packet processing circuitry to the first format associated with the emulated software device and provide, to the emulated device, the translated second descriptor.
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公开(公告)号：US20200210359A1
公开(公告)日：2020-07-02
申请号：US16814710
申请日：2020-03-10
Applicant: Intel Corporation
Inventor： Linden CORNETT , Eliel LOUZOUN , Anjali Singhai JAIN , Ronen Aharon HYATT , Danny VOLKIND , Noam ELATI , Nadav TURBOVICH
Abstract: Examples described herein relate to a device indicating a number of available interrupt messages that is more than physical resources available to store the available interrupt messages and allocating one or more physical resources to provide one or more interrupt messages based on allocation of the one or more interrupt messages to a destination entity. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level. The destination entity can request a maximum permitted allocation of interrupt messages regardless of interrupt message use level and allocate the requested maximum permitted allocation of interrupt messages for use in a configuration region of a device. However, based on unavailability of a physical resource to store a first interrupt message, allocation of the first interrupt message to a destination entity may not be permitted.
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公开(公告)号：US20190109789A1
公开(公告)日：2019-04-11
申请号：US16211385
申请日：2018-12-06
Applicant: Intel Corporation
Inventor： Ben-Zion FRIEDMAN , Eliezer TAMIR , Eliel LOUZOUN
IPC: H04L12/741 , H04L29/06 , H04L12/761 , H04L12/863
Abstract: A lower latency communications path is provided with checkpointing to verify a packet transmission is permitted. When a client initiates communication with the lower latency path, the client uses the unique tag in a packet to be transmitted. The network interface of the transmitter device can verify that the packet is an acceptable format and formed in an accepted manner. If the packet is verified, the network interface can transmit the packet to a next node according to the end-to-end configuration. The next node can read the packet's unique tag and verify the packet is an accepted format using context information associated with the unique tag. Each device in the path can perform a verification based on the tag in the packet before allow progress to a next prescribed step. A destination device can perform a verification based on the tag in the packet before allow progress to the destination receive queue.
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