公开(公告)号：US11194751B2

公开(公告)日：2021-12-07

申请号：US16513691

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Jingbo Li ,  Kai Xiao ,  Yong Yang ,  Chunfei Ye

IPC: G06F13/40 ,  G06F1/3234 ,  H04L12/40 ,  G06F5/06 ,  H03K5/24

Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

公开(公告)号：US20190044638A1

公开(公告)日：2019-02-07

申请号：US15980442

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Huimin Chen ,  David Harriman ,  Yong Yang

IPC: H04J3/16 ,  H04W52/02 ,  H04W72/04 ,  H04Q11/04

Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

公开(公告)号：US10581545B2

公开(公告)日：2020-03-03

申请号：US15980442

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Huimin Chen ,  David Harriman ,  Yong Yang

IPC: H04J3/00 ,  H04J3/16 ,  H04W52/02 ,  H04Q11/04 ,  H04W72/04 ,  H04L5/14 ,  H04L29/08

Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

公开(公告)号：US09484888B2

公开(公告)日：2016-11-01

申请号：US13719527

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Yong Yang ,  Zuoguo Wu

IPC: H03K3/00 ,  H03H11/24 ,  H03F3/45

CPC classification number: H03H11/245 ,  H03F3/45197

Abstract: Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.

Abstract translation: 描述了一种装置，包括：第一电压跟随器; 第二电压跟随器; 以及包括与n型晶体管并联的p型晶体管的通过栅极，其中p型晶体管的栅极端子由第一电压跟随器的输出控制，并且其中n型晶体管的栅极端子 由第二电压跟随器的输出控制。

公开(公告)号：US20190340146A1

公开(公告)日：2019-11-07

申请号：US16513691

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Jingbo Li ,  Kai Xiao ,  Yong Yang ,  Chunfei Ye

IPC: G06F13/40 ,  G06F1/3234 ,  H03K5/24 ,  G06F5/06 ,  H04L12/40

Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.

公开(公告)号：US11194375B2

公开(公告)日：2021-12-07

申请号：US15836281

申请日：2017-12-08

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Abdul Ismail ,  Karthi Vadivelu ,  Yong Yang

IPC: G06F1/3215 ,  G06F13/38 ,  H04L12/40 ,  G06F3/06 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/26

Abstract: An apparatus to transfer data via a communication link comprises a power bus interface to a power bus of the communication link; at least one data lane transmitter and receiver pair configured to transfer data via a data lane of the communication link; and a power bus data transmitter and receiver pair configured to transfer data via the power bus using pulse width modulation of a data signal on the power bus.