公开(公告)号：US11281597B2

公开(公告)日：2022-03-22

申请号：US15792538

申请日：2017-10-24

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Karthi R. Vadivelu ,  Abdul R. Ismail ,  Raul Gutierrez

IPC: G06F13/10 ,  G06F13/28 ,  G06F13/40 ,  H04N5/232 ,  H04N7/14 ,  G06F13/38 ,  H04N7/18 ,  G06F13/42

Abstract: Embodiments of the present disclosure are directed toward a universal serial bus (USB) device and a USB host controller. The USB device and USB host controller may be configured to couple to one another via a USB link that may include a high-speed data line and a low-speed data line. The USB device may then transmit, via the high-speed data line, an indication of a digital image to the USB host controller. Other embodiments may be described and/or claimed.

公开(公告)号：US20220014304A1

公开(公告)日：2022-01-13

申请号：US17482686

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Howard Heck ,  Huimin Chen ,  Marko Balogh

IPC: H04L1/00

Abstract: In one embodiment, an apparatus includes: a transmitter to receive application-specific data and protocol information and to send the application-specific data and the protocol information to a destination circuit via a link; and a protocol engine coupled to the transmitter, where the protocol engine is to cause the transmitter to send the application-specific data according to a first bit error rate (BER) and send the protocol information according to a second BER, the first BER greater than the second BER. Other embodiments are described and claimed.

公开(公告)号：US10581545B2

公开(公告)日：2020-03-03

申请号：US15980442

申请日：2018-05-15

Applicant: Intel Corporation

Inventor： Huimin Chen ,  David Harriman ,  Yong Yang

IPC: H04J3/00 ,  H04J3/16 ,  H04W52/02 ,  H04Q11/04 ,  H04W72/04 ,  H04L5/14 ,  H04L29/08

Abstract: An apparatus is provided, where the apparatus may include a first terminal and a second terminal to be coupled to a host via a first wire and a second wire, respectively; a rechargeable storage; and a data circuitry. The apparatus may, during a first time-period, receive power via the first wire and the second wire from the host, and store the power in the rechargeable storage, and during a second time-period, transmit data from the data circuitry to the host via the first wire and the second wire. The first and second time-periods may be non-overlapping time periods. The apparatus is to refrain from transmitting any data to, or receiving any data from, the host during the first time period.

公开(公告)号：US10235327B2

公开(公告)日：2019-03-19

申请号：US15607371

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US10223324B2

公开(公告)日：2019-03-05

申请号：US15607362

申请日：2017-05-26

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Duane G. Quiet

IPC: G06F13/00 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42

Abstract: A system and method is described for simplifying implementation of repeater (e.g., re-driver/re-timer) module implementation in high-data-rate interconnects that carry a relatively low-data-rate clock signal as well as the data stream (e.g., PCIe). At the endpoint, any information critical to the function of the repeater (e.g., the most recent data rate negotiated by a pair of endpoints communicating through the repeater) is embedded in the clock signal by pulse-width modulation as ordered sets. The repeater only needs to read the clock-embedded information rather than decoding the data stream. Thus repeaters for such applications reconstruct the high-rate data-stream while actually decoding only the low-rate clock signal. Because the clock-signal protocol is independent of the data-stream protocol, the repeater's operation is protocol-agnostic with respect to the data-stream.

公开(公告)号：US09606955B2

公开(公告)日：2017-03-28

申请号：US14457594

申请日：2014-08-12

Applicant: INTEL CORPORATION

Inventor： Huimin Chen ,  Jia Jun Lee ,  Amit Kumar Srivastava ,  Teong Guan T. G. Yew ,  Tim McKee

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/4291 ,  G06F13/385

Abstract: Techniques for embedded high speed serial interface methods are described herein. The method includes issuing a single-ended one (SE1) signal on each of a pair of embedded high speed serial interface data lines, the SE1 indicating a register access protocol (RAP) message follows the SE1 signal. The method also includes accessing a register of an embedded high speed serial interface component based on the RAP message.

公开(公告)号：US09348781B2

公开(公告)日：2016-05-24

申请号：US13730657

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Kok Hong Chan ,  Huimin Chen

IPC: G06F3/00 ,  G06F13/38 ,  G06F11/30 ,  G06F13/12

CPC classification number: G06F13/385 ,  G06F1/266 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3253 ,  G06F11/3041 ,  G06F11/3051 ,  G06F11/3055 ,  G06F13/4282 ,  G06F2213/0042 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods for operating a universal serial bus are described herein. The method includes sending packet data from a USB2 device to a USB2 host on a pair of signal lines, and after sending the packet data, sending an End-Of-Packet (EOP) signal from the USB2 device to the USB2 host. The method also includes, entering the USB2 device into idle state after sending the EOP signal. The method also includes sending a digital ping from the USB2 device to the USB2 host to indicate device presence during idle state.

公开(公告)号：US20150378952A1

公开(公告)日：2015-12-31

申请号：US14317874

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Howard L. Heck

IPC: G06F13/42

CPC classification number: G06F13/423 ,  G05B2219/25181 ,  G06F13/4045 ,  G06F13/4256 ,  G06F2213/0052 ,  H04B3/58 ,  H04B10/29 ,  H04B2203/5479 ,  Y02B70/123 ,  Y02B70/126 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus for retimer presence detection is described herein. The apparatus includes at least one retimer, wherein an algorithm is to enable the at least one retimer to announce its presence by asserting a bit of a presence message during link initialization. The at least one retimer can declare an index and is accessible via the index.

Abstract translation: 本文描述了重新定时器存在检测的装置。 该装置包括至少一个重定时器，其中算法是使得至少一个重定时器通过在链路初始化期间断言存在消息的位来通知其存在。 至少一个重定时器可以声明一个索引并且可以通过索引访问。

公开(公告)号：US09104817B2

公开(公告)日：2015-08-11

申请号：US13730370

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Kok Hong Chan

IPC: H04B3/00 ,  G06F13/38 ,  H04L25/02

CPC classification number: G06F13/385 ,  G06F1/3253 ,  G06F13/4072 ,  G06F13/4282 ,  G06F2213/0042 ,  H04L25/0272 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method for explicit control message signaling includes sending a single ended 1 signal on a pair of data lines, wherein the pair of data lines includes a first data line and a second data line. A voltage of the first data line is driven to a logic 1, while pulsing the voltage of the second data line between a logic 1 and a logic 0, wherein the pulses represent a control message.

Abstract translation: 用于显式控制消息信令的方法包括在一对数据线上发送单端1信号，其中该对数据线包括第一数据线和第二数据线。 第一数据线的电压被驱动到逻辑1，同时脉冲第二数据线的电压在逻辑1和逻辑0之间，其中脉冲表示控制消息。

公开(公告)号：US11194751B2

公开(公告)日：2021-12-07

申请号：US16513691

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Huimin Chen ,  Jingbo Li ,  Kai Xiao ,  Yong Yang ,  Chunfei Ye

IPC: G06F13/40 ,  G06F1/3234 ,  H04L12/40 ,  G06F5/06 ,  H03K5/24

Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.