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    AN APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM
    1.
    发明申请
    AN APPARATUS TO REDUCE IDLE LINK POWER IN A PLATFORM 审中-公开
    降低平台中空闲链路功率的设备

    公开(公告)号：US20160109925A1

    公开(公告)日：2016-04-21

    申请号：US14978340

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

    IPC: G06F1/32

    CPC classification number: G06F1/325 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

    Abstract: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.

    Abstract translation: 提供了一种芯片系统（SoC），包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。 根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测 电路被禁用，并且不保持共模电压。 根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

    Apparatus to reduce idle link power in a platform
    5.
    发明授权
    Apparatus to reduce idle link power in a platform 有权
    降低平台空闲链路功率的装置

    公开(公告)号：US09367116B2

    公开(公告)日：2016-06-14

    申请号：US14978340

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/325 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

    Abstract: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.

    Abstract translation: 提供了一种芯片系统（SoC），包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。 根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测 电路被禁用，并且不保持共模电压。 根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

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