公开(公告)号：US20230244609A1

公开(公告)日：2023-08-03

申请号：US18148749

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： ZACK S. WATERS ,  TRAVIS SCHLUESSLER ,  MICHAEL APODACA ,  ANKUR SHAH

IPC: G06F12/0882 ,  G06F12/0837 ,  G06F12/1045 ,  G06F11/30 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/06

CPC classification number: G06F12/0882 ,  G06F12/0837 ,  G06F12/1054 ,  G06F12/1063 ,  G06F11/3006 ,  G06F9/5016 ,  G06F9/4411 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0607

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

公开(公告)号：US20210263853A1

公开(公告)日：2021-08-26

申请号：US16802427

申请日：2020-02-26

Applicant: Intel Corporation

Inventor： ZACK S. WATERS ,  TRAVIS SCHLUESSLER ,  MICHAEL APODACA ,  ANKUR SHAH

IPC: G06F12/0882 ,  G06F12/0837 ,  G06F12/1045 ,  G06F12/06 ,  G06F9/50 ,  G06F9/4401 ,  G06F9/54 ,  G06F11/30

Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.

公开(公告)号：US20160140684A1

公开(公告)日：2016-05-19

申请号：US14542571

申请日：2014-11-15

Applicant: Intel Corporation

Inventor： JASON M. SURPRISE ,  ZACK S. WATERS

IPC: G06T1/20 ,  G09G5/36 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G09G5/363

Abstract: Methods and apparatus relating to sort-free threading model for a multi-threaded graphics pipeline are described. In an embodiment, draw requests, corresponding to one or more primitives in an image, are stored in entries of a queue (e.g., in the order received). Each entry remains locked until both a front-end and a back-end of a graphics pipeline have completed one or more operations associated with the draw request. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与多线程图形管线的无排序线程模型有关的方法和装置。 在一个实施例中，对应于图像中的一个或多个图元的绘制请求被存储在队列的条目中（例如，以接收的顺序）。 每个条目保持锁定，直到图形流水线的前端和后端完成与绘图请求相关联的一个或多个操作。 还公开并要求保护其他实施例。